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authorTomi Valkeinen <tomi.valkeinen@ti.com>2012-10-15 14:27:04 +0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-11-05 13:14:05 +0400
commit930b027eb41e31e86618ecd06cf4acf1e44c136b (patch)
tree6f4285a438e9280aacdcaa82834a97cfbb910752 /drivers/video/omap2/dss/dss.c
parent7a98786caa18eaa8a5e61382a575f0b6c8e81c01 (diff)
downloadlinux-930b027eb41e31e86618ecd06cf4acf1e44c136b.tar.xz
OMAPDSS: add dss_calc_clock_rates() back
dss_calc_clock_rates() was removed earlier as it was not used, but it is needed for DSI PLL calculations, so this patch adds it back. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss.c')
-rw-r--r--drivers/video/omap2/dss/dss.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 456118beb1f8..d40653bf7a6c 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -432,6 +432,29 @@ enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
}
}
+/* calculate clock rates using dividers in cinfo */
+int dss_calc_clock_rates(struct dss_clock_info *cinfo)
+{
+ if (dss.dpll4_m4_ck) {
+ unsigned long prate;
+
+ if (cinfo->fck_div > dss.feat->fck_div_max ||
+ cinfo->fck_div == 0)
+ return -EINVAL;
+
+ prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
+
+ cinfo->fck = prate / cinfo->fck_div *
+ dss.feat->dss_fck_multiplier;
+ } else {
+ if (cinfo->fck_div != 0)
+ return -EINVAL;
+ cinfo->fck = clk_get_rate(dss.dss_clk);
+ }
+
+ return 0;
+}
+
int dss_set_clock_div(struct dss_clock_info *cinfo)
{
if (dss.dpll4_m4_ck) {