video: move fbdev to drivers/video/fbdev

The drivers/video directory is a mess. It contains generic video related
files, directories for backlight, console, linux logo, lots of fbdev
device drivers, fbdev framework files.

Make some order into the chaos by creating drivers/video/fbdev
directory, and move all fbdev related files there.

No functionality is changed, although I guess it is possible that some
subtle Makefile build order related issue could be created by this
patch.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>

7 files changed, 0 insertions, 2240 deletions

diff --git a/drivers/video/mb862xx/Makefile b/drivers/video/mb862xx/Makefile
deleted file mode 100644
index 5707ed0e31a7..000000000000
--- a/drivers/video/mb862xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the MB862xx framebuffer driver
-#
-
-obj-$(CONFIG_FB_MB862XX) += mb862xxfb.o
-
-mb862xxfb-y := mb862xxfbdrv.o mb862xxfb_accel.o
-mb862xxfb-$(CONFIG_FB_MB862XX_I2C) += mb862xx-i2c.o
diff --git a/drivers/video/mb862xx/mb862xx-i2c.c b/drivers/video/mb862xx/mb862xx-i2c.c
deleted file mode 100644
index c87e17afb3e2..000000000000
--- a/drivers/video/mb862xx/mb862xx-i2c.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Coral-P(A)/Lime I2C adapter driver
- *
- * (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/fb.h>
-#include <linux/i2c.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-
-#include "mb862xxfb.h"
-#include "mb862xx_reg.h"
-
-static int mb862xx_i2c_wait_event(struct i2c_adapter *adap)
-{
-	struct mb862xxfb_par *par = adap->algo_data;
-	u32 reg;
-
-	do {
-		udelay(10);
-		reg = inreg(i2c, GC_I2C_BCR);
-		if (reg & (I2C_INT | I2C_BER))
-			break;
-	} while (1);
-
-	return (reg & I2C_BER) ? 0 : 1;
-}
-
-static int mb862xx_i2c_do_address(struct i2c_adapter *adap, int addr)
-{
-	struct mb862xxfb_par *par = adap->algo_data;
-
-	outreg(i2c, GC_I2C_DAR, addr);
-	outreg(i2c, GC_I2C_CCR, I2C_CLOCK_AND_ENABLE);
-	outreg(i2c, GC_I2C_BCR, par->i2c_rs ? I2C_REPEATED_START : I2C_START);
-	if (!mb862xx_i2c_wait_event(adap))
-		return -EIO;
-	par->i2c_rs = !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
-	return par->i2c_rs;
-}
-
-static int mb862xx_i2c_write_byte(struct i2c_adapter *adap, u8 byte)
-{
-	struct mb862xxfb_par *par = adap->algo_data;
-
-	outreg(i2c, GC_I2C_DAR, byte);
-	outreg(i2c, GC_I2C_BCR, I2C_START);
-	if (!mb862xx_i2c_wait_event(adap))
-		return -EIO;
-	return !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
-}
-
-static int mb862xx_i2c_read_byte(struct i2c_adapter *adap, u8 *byte, int last)
-{
-	struct mb862xxfb_par *par = adap->algo_data;
-
-	outreg(i2c, GC_I2C_BCR, I2C_START | (last ? 0 : I2C_ACK));
-	if (!mb862xx_i2c_wait_event(adap))
-		return 0;
-	*byte = inreg(i2c, GC_I2C_DAR);
-	return 1;
-}
-
-static void mb862xx_i2c_stop(struct i2c_adapter *adap)
-{
-	struct mb862xxfb_par *par = adap->algo_data;
-
-	outreg(i2c, GC_I2C_BCR, I2C_STOP);
-	outreg(i2c, GC_I2C_CCR, I2C_DISABLE);
-	par->i2c_rs = 0;
-}
-
-static int mb862xx_i2c_read(struct i2c_adapter *adap, struct i2c_msg *m)
-{
-	int i, ret = 0;
-	int last = m->len - 1;
-
-	for (i = 0; i < m->len; i++) {
-		if (!mb862xx_i2c_read_byte(adap, &m->buf[i], i == last)) {
-			ret = -EIO;
-			break;
-		}
-	}
-	return ret;
-}
-
-static int mb862xx_i2c_write(struct i2c_adapter *adap, struct i2c_msg *m)
-{
-	int i, ret = 0;
-
-	for (i = 0; i < m->len; i++) {
-		if (!mb862xx_i2c_write_byte(adap, m->buf[i])) {
-			ret = -EIO;
-			break;
-		}
-	}
-	return ret;
-}
-
-static int mb862xx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
-			int num)
-{
-	struct mb862xxfb_par *par = adap->algo_data;
-	struct i2c_msg *m;
-	int addr;
-	int i = 0, err = 0;
-
-	dev_dbg(par->dev, "%s: %d msgs\n", __func__, num);
-
-	for (i = 0; i < num; i++) {
-		m = &msgs[i];
-		if (!m->len) {
-			dev_dbg(par->dev, "%s: null msgs\n", __func__);
-			continue;
-		}
-		addr = m->addr;
-		if (m->flags & I2C_M_RD)
-			addr |= 1;
-
-		err = mb862xx_i2c_do_address(adap, addr);
-		if (err < 0)
-			break;
-		if (m->flags & I2C_M_RD)
-			err = mb862xx_i2c_read(adap, m);
-		else
-			err = mb862xx_i2c_write(adap, m);
-	}
-
-	if (i)
-		mb862xx_i2c_stop(adap);
-
-	return (err < 0) ? err : i;
-}
-
-static u32 mb862xx_func(struct i2c_adapter *adap)
-{
-	return I2C_FUNC_SMBUS_BYTE_DATA;
-}
-
-static const struct i2c_algorithm mb862xx_algo = {
-	.master_xfer	= mb862xx_xfer,
-	.functionality	= mb862xx_func,
-};
-
-static struct i2c_adapter mb862xx_i2c_adapter = {
-	.name		= "MB862xx I2C adapter",
-	.algo		= &mb862xx_algo,
-	.owner		= THIS_MODULE,
-};
-
-int mb862xx_i2c_init(struct mb862xxfb_par *par)
-{
-	int ret;
-
-	mb862xx_i2c_adapter.algo_data = par;
-	par->adap = &mb862xx_i2c_adapter;
-
-	ret = i2c_add_adapter(par->adap);
-	if (ret < 0) {
-		dev_err(par->dev, "failed to add %s\n",
-			mb862xx_i2c_adapter.name);
-	}
-	return ret;
-}
-
-void mb862xx_i2c_exit(struct mb862xxfb_par *par)
-{
-	if (par->adap) {
-		i2c_del_adapter(par->adap);
-		par->adap = NULL;
-	}
-}
diff --git a/drivers/video/mb862xx/mb862xx_reg.h b/drivers/video/mb862xx/mb862xx_reg.h
deleted file mode 100644
index 9df48b8edc94..000000000000
--- a/drivers/video/mb862xx/mb862xx_reg.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Fujitsu MB862xx Graphics Controller Registers/Bits
- */
-
-#ifndef _MB862XX_REG_H
-#define _MB862XX_REG_H
-
-#define MB862XX_MMIO_BASE	0x01fc0000
-#define MB862XX_MMIO_HIGH_BASE	0x03fc0000
-#define MB862XX_I2C_BASE	0x0000c000
-#define MB862XX_DISP_BASE	0x00010000
-#define MB862XX_CAP_BASE	0x00018000
-#define MB862XX_DRAW_BASE	0x00030000
-#define MB862XX_GEO_BASE	0x00038000
-#define MB862XX_PIO_BASE	0x00038000
-#define MB862XX_MMIO_SIZE	0x40000
-
-/* Host interface/pio registers */
-#define GC_IST			0x00000020
-#define GC_IMASK		0x00000024
-#define GC_SRST			0x0000002c
-#define GC_CCF			0x00000038
-#define GC_RSW			0x0000005c
-#define GC_CID			0x000000f0
-#define GC_REVISION		0x00000084
-
-#define GC_CCF_CGE_100		0x00000000
-#define GC_CCF_CGE_133		0x00040000
-#define GC_CCF_CGE_166		0x00080000
-#define GC_CCF_COT_100		0x00000000
-#define GC_CCF_COT_133		0x00010000
-#define GC_CID_CNAME_MSK	0x0000ff00
-#define GC_CID_VERSION_MSK	0x000000ff
-
-/* define enabled interrupts hereby */
-#define GC_INT_EN		0x00000000
-
-/* Memory interface mode register */
-#define GC_MMR			0x0000fffc
-
-/* Display Controller registers */
-#define GC_DCM0			0x00000000
-#define GC_HTP			0x00000004
-#define GC_HDB_HDP		0x00000008
-#define GC_VSW_HSW_HSP		0x0000000c
-#define GC_VTR			0x00000010
-#define GC_VDP_VSP		0x00000014
-#define GC_WY_WX		0x00000018
-#define GC_WH_WW		0x0000001c
-#define GC_L0M			0x00000020
-#define GC_L0OA0		0x00000024
-#define GC_L0DA0		0x00000028
-#define GC_L0DY_L0DX		0x0000002c
-#define GC_L1M			0x00000030
-#define GC_L1DA			0x00000034
-#define GC_DCM1			0x00000100
-#define GC_L0EM			0x00000110
-#define GC_L0WY_L0WX		0x00000114
-#define GC_L0WH_L0WW		0x00000118
-#define GC_L1EM			0x00000120
-#define GC_L1WY_L1WX		0x00000124
-#define GC_L1WH_L1WW		0x00000128
-#define GC_DLS			0x00000180
-#define GC_DCM2			0x00000104
-#define GC_DCM3			0x00000108
-#define GC_CPM_CUTC		0x000000a0
-#define GC_CUOA0		0x000000a4
-#define GC_CUY0_CUX0		0x000000a8
-#define GC_CUOA1		0x000000ac
-#define GC_CUY1_CUX1		0x000000b0
-#define GC_L0PAL0		0x00000400
-
-#define GC_CPM_CEN0		0x00100000
-#define GC_CPM_CEN1		0x00200000
-#define GC_DCM1_DEN		0x80000000
-#define GC_DCM1_L1E		0x00020000
-#define GC_L1M_16		0x80000000
-#define GC_L1M_YC		0x40000000
-#define GC_L1M_CS		0x20000000
-
-#define GC_DCM01_ESY		0x00000004
-#define GC_DCM01_SC		0x00003f00
-#define GC_DCM01_RESV		0x00004000
-#define GC_DCM01_CKS		0x00008000
-#define GC_DCM01_L0E		0x00010000
-#define GC_DCM01_DEN		0x80000000
-#define GC_L0M_L0C_8		0x00000000
-#define GC_L0M_L0C_16		0x80000000
-#define GC_L0EM_L0EC_24		0x40000000
-#define GC_L0M_L0W_UNIT		64
-#define GC_L1EM_DM		0x02000000
-
-#define GC_DISP_REFCLK_400	400
-
-/* I2C */
-#define GC_I2C_BSR		0x00000000	/* BSR */
-#define GC_I2C_BCR		0x00000004	/* BCR */
-#define GC_I2C_CCR		0x00000008	/* CCR */
-#define GC_I2C_ADR		0x0000000C	/* ADR */
-#define GC_I2C_DAR		0x00000010	/* DAR */
-
-#define I2C_DISABLE		0x00000000
-#define I2C_STOP		0x00000000
-#define I2C_START		0x00000010
-#define I2C_REPEATED_START	0x00000030
-#define I2C_CLOCK_AND_ENABLE	0x0000003f
-#define I2C_READY		0x01
-#define I2C_INT			0x01
-#define I2C_INTE		0x02
-#define I2C_ACK			0x08
-#define I2C_BER			0x80
-#define I2C_BEIE		0x40
-#define I2C_TRX			0x80
-#define I2C_LRB			0x10
-
-/* Capture registers and bits */
-#define GC_CAP_VCM		0x00000000
-#define GC_CAP_CSC		0x00000004
-#define GC_CAP_VCS		0x00000008
-#define GC_CAP_CBM		0x00000010
-#define GC_CAP_CBOA		0x00000014
-#define GC_CAP_CBLA		0x00000018
-#define GC_CAP_IMG_START	0x0000001C
-#define GC_CAP_IMG_END		0x00000020
-#define GC_CAP_CMSS		0x00000048
-#define GC_CAP_CMDS		0x0000004C
-
-#define GC_VCM_VIE		0x80000000
-#define GC_VCM_CM		0x03000000
-#define GC_VCM_VS_PAL		0x00000002
-#define GC_CBM_OO		0x80000000
-#define GC_CBM_HRV		0x00000010
-#define GC_CBM_CBST		0x00000001
-
-/* Carmine specific */
-#define MB86297_DRAW_BASE		0x00020000
-#define MB86297_DISP0_BASE		0x00100000
-#define MB86297_DISP1_BASE		0x00140000
-#define MB86297_WRBACK_BASE		0x00180000
-#define MB86297_CAP0_BASE		0x00200000
-#define MB86297_CAP1_BASE		0x00280000
-#define MB86297_DRAMCTRL_BASE		0x00300000
-#define MB86297_CTRL_BASE		0x00400000
-#define MB86297_I2C_BASE		0x00500000
-
-#define GC_CTRL_STATUS			0x00000000
-#define GC_CTRL_INT_MASK		0x00000004
-#define GC_CTRL_CLK_ENABLE		0x0000000c
-#define GC_CTRL_SOFT_RST		0x00000010
-
-#define GC_CTRL_CLK_EN_DRAM		0x00000001
-#define GC_CTRL_CLK_EN_2D3D		0x00000002
-#define GC_CTRL_CLK_EN_DISP0		0x00000020
-#define GC_CTRL_CLK_EN_DISP1		0x00000040
-
-#define GC_2D3D_REV			0x000004b4
-#define GC_RE_REVISION			0x24240200
-
-/* define enabled interrupts hereby */
-#define GC_CARMINE_INT_EN		0x00000004
-
-/* DRAM controller */
-#define GC_DCTL_MODE_ADD		0x00000000
-#define GC_DCTL_SETTIME1_EMODE		0x00000004
-#define GC_DCTL_REFRESH_SETTIME2	0x00000008
-#define GC_DCTL_RSV0_STATES		0x0000000C
-#define GC_DCTL_RSV2_RSV1		0x00000010
-#define GC_DCTL_DDRIF2_DDRIF1		0x00000014
-#define GC_DCTL_IOCONT1_IOCONT0		0x00000024
-
-#define GC_DCTL_STATES_MSK		0x0000000f
-#define GC_DCTL_INIT_WAIT_CNT		3000
-#define GC_DCTL_INIT_WAIT_INTERVAL	1
-
-/* DRAM ctrl values for Carmine PCI Eval. board */
-#define GC_EVB_DCTL_MODE_ADD		0x012105c3
-#define GC_EVB_DCTL_MODE_ADD_AFT_RST	0x002105c3
-#define GC_EVB_DCTL_SETTIME1_EMODE	0x47498000
-#define GC_EVB_DCTL_REFRESH_SETTIME2	0x00422a22
-#define GC_EVB_DCTL_RSV0_STATES		0x00200003
-#define GC_EVB_DCTL_RSV0_STATES_AFT_RST	0x00200002
-#define GC_EVB_DCTL_RSV2_RSV1		0x0000000f
-#define GC_EVB_DCTL_DDRIF2_DDRIF1	0x00556646
-#define GC_EVB_DCTL_IOCONT1_IOCONT0	0x05550555
-
-#define GC_DISP_REFCLK_533		533
-
-#endif
diff --git a/drivers/video/mb862xx/mb862xxfb.h b/drivers/video/mb862xx/mb862xxfb.h
deleted file mode 100644
index 8550630c1e01..000000000000
--- a/drivers/video/mb862xx/mb862xxfb.h
+++ /dev/null
@@ -1,121 +0,0 @@
-#ifndef __MB862XX_H__
-#define __MB862XX_H__
-
-struct mb862xx_l1_cfg {
-	unsigned short sx;
-	unsigned short sy;
-	unsigned short sw;
-	unsigned short sh;
-	unsigned short dx;
-	unsigned short dy;
-	unsigned short dw;
-	unsigned short dh;
-	int mirror;
-};
-
-#define MB862XX_BASE		'M'
-#define MB862XX_L1_GET_CFG	_IOR(MB862XX_BASE, 0, struct mb862xx_l1_cfg*)
-#define MB862XX_L1_SET_CFG	_IOW(MB862XX_BASE, 1, struct mb862xx_l1_cfg*)
-#define MB862XX_L1_ENABLE	_IOW(MB862XX_BASE, 2, int)
-#define MB862XX_L1_CAP_CTL	_IOW(MB862XX_BASE, 3, int)
-
-#ifdef __KERNEL__
-
-#define PCI_VENDOR_ID_FUJITSU_LIMITED	0x10cf
-#define PCI_DEVICE_ID_FUJITSU_CORALP	0x2019
-#define PCI_DEVICE_ID_FUJITSU_CORALPA	0x201e
-#define PCI_DEVICE_ID_FUJITSU_CARMINE	0x202b
-
-#define GC_MMR_CORALP_EVB_VAL		0x11d7fa13
-
-enum gdctype {
-	BT_NONE,
-	BT_LIME,
-	BT_MINT,
-	BT_CORAL,
-	BT_CORALP,
-	BT_CARMINE,
-};
-
-struct mb862xx_gc_mode {
-	struct fb_videomode	def_mode;	/* mode of connected display */
-	unsigned int		def_bpp;	/* default depth */
-	unsigned long		max_vram;	/* connected SDRAM size */
-	unsigned long		ccf;		/* gdc clk */
-	unsigned long		mmr;		/* memory mode for SDRAM */
-};
-
-/* private data */
-struct mb862xxfb_par {
-	struct fb_info		*info;		/* fb info head */
-	struct device		*dev;
-	struct pci_dev		*pdev;
-	struct resource		*res;		/* framebuffer/mmio resource */
-
-	resource_size_t		fb_base_phys;	/* fb base, 36-bit PPC440EPx */
-	resource_size_t		mmio_base_phys;	/* io base addr */
-	void __iomem		*fb_base;	/* remapped framebuffer */
-	void __iomem		*mmio_base;	/* remapped registers */
-	size_t			mapped_vram;	/* length of remapped vram */
-	size_t			mmio_len;	/* length of register region */
-	unsigned long		cap_buf;	/* capture buffers offset */
-	size_t			cap_len;	/* length of capture buffers */
-
-	void __iomem		*host;		/* relocatable reg. bases */
-	void __iomem		*i2c;
-	void __iomem		*disp;
-	void __iomem		*disp1;
-	void __iomem		*cap;
-	void __iomem		*cap1;
-	void __iomem		*draw;
-	void __iomem		*geo;
-	void __iomem		*pio;
-	void __iomem		*ctrl;
-	void __iomem		*dram_ctrl;
-	void __iomem		*wrback;
-
-	unsigned int		irq;
-	unsigned int		type;		/* GDC type */
-	unsigned int		refclk;		/* disp. reference clock */
-	struct mb862xx_gc_mode	*gc_mode;	/* GDC mode init data */
-	int			pre_init;	/* don't init display if 1 */
-	struct i2c_adapter	*adap;		/* GDC I2C bus adapter */
-	int			i2c_rs;
-
-	struct mb862xx_l1_cfg	l1_cfg;
-	int			l1_stride;
-
-	u32			pseudo_palette[16];
-};
-
-extern void mb862xxfb_init_accel(struct fb_info *info, int xres);
-#ifdef CONFIG_FB_MB862XX_I2C
-extern int mb862xx_i2c_init(struct mb862xxfb_par *par);
-extern void mb862xx_i2c_exit(struct mb862xxfb_par *par);
-#else
-static inline int mb862xx_i2c_init(struct mb862xxfb_par *par) { return 0; }
-static inline void mb862xx_i2c_exit(struct mb862xxfb_par *par) { }
-#endif
-
-#if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC)
-#error	"Select Lime GDC or CoralP/Carmine support, but not both together"
-#endif
-#if defined(CONFIG_FB_MB862XX_LIME)
-#define gdc_read	__raw_readl
-#define gdc_write	__raw_writel
-#else
-#define gdc_read	readl
-#define gdc_write	writel
-#endif
-
-#define inreg(type, off)	\
-	gdc_read((par->type + (off)))
-
-#define outreg(type, off, val)	\
-	gdc_write((val), (par->type + (off)))
-
-#define pack(a, b)	(((a) << 16) | (b))
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/drivers/video/mb862xx/mb862xxfb_accel.c b/drivers/video/mb862xx/mb862xxfb_accel.c
deleted file mode 100644
index fe92eed6da70..000000000000
--- a/drivers/video/mb862xx/mb862xxfb_accel.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * drivers/mb862xx/mb862xxfb_accel.c
- *
- * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver acceleration support
- *
- * (C) 2007 Alexander Shishkin <virtuoso@slind.org>
- * (C) 2009 Valentin Sitdikov <v.sitdikov@gmail.com>
- * (C) 2009 Siemens AG
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/fb.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#if defined(CONFIG_OF)
-#include <linux/of_platform.h>
-#endif
-#include "mb862xxfb.h"
-#include "mb862xx_reg.h"
-#include "mb862xxfb_accel.h"
-
-static void mb862xxfb_write_fifo(u32 count, u32 *data, struct fb_info *info)
-{
-	struct mb862xxfb_par *par = info->par;
-	static u32 free;
-
-	u32 total = 0;
-	while (total < count) {
-		if (free) {
-			outreg(geo, GDC_GEO_REG_INPUT_FIFO, data[total]);
-			total++;
-			free--;
-		} else {
-			free = (u32) inreg(draw, GDC_REG_FIFO_COUNT);
-		}
-	}
-}
-
-static void mb86290fb_copyarea(struct fb_info *info,
-			       const struct fb_copyarea *area)
-{
-	__u32 cmd[6];
-
-	cmd[0] = (GDC_TYPE_SETREGISTER << 24) | (1 << 16) | GDC_REG_MODE_BITMAP;
-	/* Set raster operation */
-	cmd[1] = (2 << 7) | (GDC_ROP_COPY << 9);
-	cmd[2] = GDC_TYPE_BLTCOPYP << 24;
-
-	if (area->sx >= area->dx && area->sy >= area->dy)
-		cmd[2] |= GDC_CMD_BLTCOPY_TOP_LEFT << 16;
-	else if (area->sx >= area->dx && area->sy <= area->dy)
-		cmd[2] |= GDC_CMD_BLTCOPY_BOTTOM_LEFT << 16;
-	else if (area->sx <= area->dx && area->sy >= area->dy)
-		cmd[2] |= GDC_CMD_BLTCOPY_TOP_RIGHT << 16;
-	else
-		cmd[2] |= GDC_CMD_BLTCOPY_BOTTOM_RIGHT << 16;
-
-	cmd[3] = (area->sy << 16) | area->sx;
-	cmd[4] = (area->dy << 16) | area->dx;
-	cmd[5] = (area->height << 16) | area->width;
-	mb862xxfb_write_fifo(6, cmd, info);
-}
-
-/*
- * Fill in the cmd array /GDC FIFO commands/ to draw a 1bit image.
- * Make sure cmd has enough room!
- */
-static void mb86290fb_imageblit1(u32 *cmd, u16 step, u16 dx, u16 dy,
-				 u16 width, u16 height, u32 fgcolor,
-				 u32 bgcolor, const struct fb_image *image,
-				 struct fb_info *info)
-{
-	int i;
-	unsigned const char *line;
-	u16 bytes;
-
-	/* set colors and raster operation regs */
-	cmd[0] = (GDC_TYPE_SETREGISTER << 24) | (1 << 16) | GDC_REG_MODE_BITMAP;
-	/* Set raster operation */
-	cmd[1] = (2 << 7) | (GDC_ROP_COPY << 9);
-	cmd[2] =
-	    (GDC_TYPE_SETCOLORREGISTER << 24) | (GDC_CMD_BODY_FORE_COLOR << 16);
-	cmd[3] = fgcolor;
-	cmd[4] =
-	    (GDC_TYPE_SETCOLORREGISTER << 24) | (GDC_CMD_BODY_BACK_COLOR << 16);
-	cmd[5] = bgcolor;
-
-	i = 0;
-	line = image->data;
-	bytes = (image->width + 7) >> 3;
-
-	/* and the image */
-	cmd[6] = (GDC_TYPE_DRAWBITMAPP << 24) |
-	    (GDC_CMD_BITMAP << 16) | (2 + (step * height));
-	cmd[7] = (dy << 16) | dx;
-	cmd[8] = (height << 16) | width;
-
-	while (i < height) {
-		memcpy(&cmd[9 + i * step], line, step << 2);
-#ifdef __LITTLE_ENDIAN
-		{
-			int k = 0;
-			for (k = 0; k < step; k++)
-				cmd[9 + i * step + k] =
-				    cpu_to_be32(cmd[9 + i * step + k]);
-		}
-#endif
-		line += bytes;
-		i++;
-	}
-}
-
-/*
- * Fill in the cmd array /GDC FIFO commands/ to draw a 8bit image.
- * Make sure cmd has enough room!
- */
-static void mb86290fb_imageblit8(u32 *cmd, u16 step, u16 dx, u16 dy,
-				 u16 width, u16 height, u32 fgcolor,
-				 u32 bgcolor, const struct fb_image *image,
-				 struct fb_info *info)
-{
-	int i, j;
-	unsigned const char *line, *ptr;
-	u16 bytes;
-
-	cmd[0] = (GDC_TYPE_DRAWBITMAPP << 24) |
-	    (GDC_CMD_BLT_DRAW << 16) | (2 + (height * step));
-	cmd[1] = (dy << 16) | dx;
-	cmd[2] = (height << 16) | width;
-
-	i = 0;
-	line = ptr = image->data;
-	bytes = image->width;
-
-	while (i < height) {
-		ptr = line;
-		for (j = 0; j < step; j++) {
-			cmd[3 + i * step + j] =
-			    (((u32 *) (info->pseudo_palette))[*ptr]) & 0xffff;
-			ptr++;
-			cmd[3 + i * step + j] |=
-			    ((((u32 *) (info->
-					pseudo_palette))[*ptr]) & 0xffff) << 16;
-			ptr++;
-		}
-
-		line += bytes;
-		i++;
-	}
-}
-
-/*
- * Fill in the cmd array /GDC FIFO commands/ to draw a 16bit image.
- * Make sure cmd has enough room!
- */
-static void mb86290fb_imageblit16(u32 *cmd, u16 step, u16 dx, u16 dy,
-				  u16 width, u16 height, u32 fgcolor,
-				  u32 bgcolor, const struct fb_image *image,
-				  struct fb_info *info)
-{
-	int i;
-	unsigned const char *line;
-	u16 bytes;
-
-	i = 0;
-	line = image->data;
-	bytes = image->width << 1;
-
-	cmd[0] = (GDC_TYPE_DRAWBITMAPP << 24) |
-	    (GDC_CMD_BLT_DRAW << 16) | (2 + step * height);
-	cmd[1] = (dy << 16) | dx;
-	cmd[2] = (height << 16) | width;
-
-	while (i < height) {
-		memcpy(&cmd[3 + i * step], line, step);
-		line += bytes;
-		i++;
-	}
-}
-
-static void mb86290fb_imageblit(struct fb_info *info,
-				const struct fb_image *image)
-{
-	int mdr;
-	u32 *cmd = NULL;
-	void (*cmdfn) (u32 *, u16, u16, u16, u16, u16, u32, u32,
-		       const struct fb_image *, struct fb_info *) = NULL;
-	u32 cmdlen;
-	u32 fgcolor = 0, bgcolor = 0;
-	u16 step;
-
-	u16 width = image->width, height = image->height;
-	u16 dx = image->dx, dy = image->dy;
-	int x2, y2, vxres, vyres;
-
-	mdr = (GDC_ROP_COPY << 9);
-	x2 = image->dx + image->width;
-	y2 = image->dy + image->height;
-	vxres = info->var.xres_virtual;
-	vyres = info->var.yres_virtual;
-	x2 = min(x2, vxres);
-	y2 = min(y2, vyres);
-	width = x2 - dx;
-	height = y2 - dy;
-
-	switch (image->depth) {
-	case 1:
-		step = (width + 31) >> 5;
-		cmdlen = 9 + height * step;
-		cmdfn = mb86290fb_imageblit1;
-		if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
-		    info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
-			fgcolor =
-			    ((u32 *) (info->pseudo_palette))[image->fg_color];
-			bgcolor =
-			    ((u32 *) (info->pseudo_palette))[image->bg_color];
-		} else {
-			fgcolor = image->fg_color;
-			bgcolor = image->bg_color;
-		}
-
-		break;
-
-	case 8:
-		step = (width + 1) >> 1;
-		cmdlen = 3 + height * step;
-		cmdfn = mb86290fb_imageblit8;
-		break;
-
-	case 16:
-		step = (width + 1) >> 1;
-		cmdlen = 3 + height * step;
-		cmdfn = mb86290fb_imageblit16;
-		break;
-
-	default:
-		cfb_imageblit(info, image);
-		return;
-	}
-
-	cmd = kmalloc(cmdlen * 4, GFP_DMA);
-	if (!cmd)
-		return cfb_imageblit(info, image);
-	cmdfn(cmd, step, dx, dy, width, height, fgcolor, bgcolor, image, info);
-	mb862xxfb_write_fifo(cmdlen, cmd, info);
-	kfree(cmd);
-}
-
-static void mb86290fb_fillrect(struct fb_info *info,
-			       const struct fb_fillrect *rect)
-{
-
-	u32 x2, y2, vxres, vyres, height, width, fg;
-	u32 cmd[7];
-
-	vxres = info->var.xres_virtual;
-	vyres = info->var.yres_virtual;
-
-	if (!rect->width || !rect->height || rect->dx > vxres
-	    || rect->dy > vyres)
-		return;
-
-	/* We could use hardware clipping but on many cards you get around
-	 * hardware clipping by writing to framebuffer directly. */
-	x2 = rect->dx + rect->width;
-	y2 = rect->dy + rect->height;
-	x2 = min(x2, vxres);
-	y2 = min(y2, vyres);
-	width = x2 - rect->dx;
-	height = y2 - rect->dy;
-	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
-	    info->fix.visual == FB_VISUAL_DIRECTCOLOR)
-		fg = ((u32 *) (info->pseudo_palette))[rect->color];
-	else
-		fg = rect->color;
-
-	switch (rect->rop) {
-
-	case ROP_XOR:
-		/* Set raster operation */
-		cmd[1] = (2 << 7) | (GDC_ROP_XOR << 9);
-		break;
-
-	case ROP_COPY:
-		/* Set raster operation */
-		cmd[1] = (2 << 7) | (GDC_ROP_COPY << 9);
-		break;
-
-	}
-
-	cmd[0] = (GDC_TYPE_SETREGISTER << 24) | (1 << 16) | GDC_REG_MODE_BITMAP;
-	/* cmd[1] set earlier */
-	cmd[2] =
-	    (GDC_TYPE_SETCOLORREGISTER << 24) | (GDC_CMD_BODY_FORE_COLOR << 16);
-	cmd[3] = fg;
-	cmd[4] = (GDC_TYPE_DRAWRECTP << 24) | (GDC_CMD_BLT_FILL << 16);
-	cmd[5] = (rect->dy << 16) | (rect->dx);
-	cmd[6] = (height << 16) | width;
-
-	mb862xxfb_write_fifo(7, cmd, info);
-}
-
-void mb862xxfb_init_accel(struct fb_info *info, int xres)
-{
-	struct mb862xxfb_par *par = info->par;
-
-	if (info->var.bits_per_pixel == 32) {
-		info->fbops->fb_fillrect = cfb_fillrect;
-		info->fbops->fb_copyarea = cfb_copyarea;
-		info->fbops->fb_imageblit = cfb_imageblit;
-	} else {
-		outreg(disp, GC_L0EM, 3);
-		info->fbops->fb_fillrect = mb86290fb_fillrect;
-		info->fbops->fb_copyarea = mb86290fb_copyarea;
-		info->fbops->fb_imageblit = mb86290fb_imageblit;
-	}
-	outreg(draw, GDC_REG_DRAW_BASE, 0);
-	outreg(draw, GDC_REG_MODE_MISC, 0x8000);
-	outreg(draw, GDC_REG_X_RESOLUTION, xres);
-
-	info->flags |=
-	    FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
-	    FBINFO_HWACCEL_IMAGEBLIT;
-	info->fix.accel = 0xff;	/*FIXME: add right define */
-}
-EXPORT_SYMBOL(mb862xxfb_init_accel);
-
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/mb862xx/mb862xxfb_accel.h b/drivers/video/mb862xx/mb862xxfb_accel.h
deleted file mode 100644
index 96a2dfef0f60..000000000000
--- a/drivers/video/mb862xx/mb862xxfb_accel.h
+++ /dev/null
@@ -1,203 +0,0 @@
-#ifndef __MB826XXFB_ACCEL_H__
-#define __MB826XXFB_ACCEL_H__
-
-/* registers */
-#define GDC_GEO_REG_INPUT_FIFO 0x00000400L
-
-/* Special Registers */
-#define GDC_REG_CTRL                0x00000400L
-#define GDC_REG_FIFO_STATUS         0x00000404L
-#define GDC_REG_FIFO_COUNT          0x00000408L
-#define GDC_REG_SETUP_STATUS        0x0000040CL
-#define GDC_REG_DDA_STATUS          0x00000410L
-#define GDC_REG_ENGINE_STATUS       0x00000414L
-#define GDC_REG_ERROR_STATUS        0x00000418L
-#define GDC_REG_MODE_MISC           0x00000420L	/* MDR0 */
-#define GDC_REG_MODE_LINE           0x00000424L	/* MDR1 */
-#define GDC_REG_MODE_POLYGON        0x00000428L	/* MDR2 */
-#define GDC_REG_MODE_TEXTURE        0x0000042CL	/* MDR3 */
-#define GDC_REG_MODE_BITMAP         0x00000430L	/* MDR4 */
-#define GDC_REG_MODE_EXTENSION      0x0000043CL	/* MDR7 */
-
-/* Configuration Registers */
-#define GDC_REG_DRAW_BASE           0x00000440L
-#define GDC_REG_X_RESOLUTION        0x00000444L
-#define GDC_REG_Z_BASE              0x00000448L
-#define GDC_REG_TEXTURE_BASE        0x0000044CL
-#define GDC_REG_POLYGON_FLAG_BASE   0x00000450L
-#define GDC_REG_CLIP_XMIN           0x00000454L
-#define GDC_REG_CLIP_XMAX           0x00000458L
-#define GDC_REG_CLIP_YMIN           0x0000045CL
-#define GDC_REG_CLIP_YMAX           0x00000460L
-#define GDC_REG_TEXURE_SIZE         0x00000464L
-#define GDC_REG_TILE_SIZE           0x00000468L
-#define GDC_REG_TEX_BUF_OFFSET      0x0000046CL
-
-/* for MB86293 or later */
-#define GDC_REG_ALPHA_MAP_BASE      0x00000474L	/* ABR */
-
-/* Constant Registers */
-#define GDC_REG_FOREGROUND_COLOR    0x00000480L
-#define GDC_REG_BACKGROUND_COLOR    0x00000484L
-#define GDC_REG_ALPHA               0x00000488L
-#define GDC_REG_LINE_PATTERN        0x0000048CL
-#define GDC_REG_TEX_BORDER_COLOR    0x00000494L
-#define GDC_REG_LINE_PATTERN_OFFSET 0x000003E0L
-
-/* Coomand Code */
-#define GDC_CMD_PIXEL                   0x00000000L
-#define GDC_CMD_PIXEL_Z                 0x00000001L
-
-#define GDC_CMD_X_VECTOR                0x00000020L
-#define GDC_CMD_Y_VECTOR                0x00000021L
-#define GDC_CMD_X_VECTOR_NOEND          0x00000022L
-#define GDC_CMD_Y_VECTOR_NOEND          0x00000023L
-#define GDC_CMD_X_VECTOR_BLPO           0x00000024L
-#define GDC_CMD_Y_VECTOR_BLPO           0x00000025L
-#define GDC_CMD_X_VECTOR_NOEND_BLPO     0x00000026L
-#define GDC_CMD_Y_VECTOR_NOEND_BLPO     0x00000027L
-#define GDC_CMD_AA_X_VECTOR             0x00000028L
-#define GDC_CMD_AA_Y_VECTOR             0x00000029L
-#define GDC_CMD_AA_X_VECTOR_NOEND       0x0000002AL
-#define GDC_CMD_AA_Y_VECTOR_NOEND       0x0000002BL
-#define GDC_CMD_AA_X_VECTOR_BLPO        0x0000002CL
-#define GDC_CMD_AA_Y_VECTOR_BLPO        0x0000002DL
-#define GDC_CMD_AA_X_VECTOR_NOEND_BLPO  0x0000002EL
-#define GDC_CMD_AA_Y_VECTOR_NOEND_BLPO  0x0000002FL
-
-#define GDC_CMD_0_VECTOR                0x00000030L
-#define GDC_CMD_1_VECTOR                0x00000031L
-#define GDC_CMD_0_VECTOR_NOEND          0x00000032L
-#define GDC_CMD_1_VECTOR_NOEND          0x00000033L
-#define GDC_CMD_0_VECTOR_BLPO           0x00000034L
-#define GDC_CMD_1_VECTOR_BLPO           0x00000035L
-#define GDC_CMD_0_VECTOR_NOEND_BLPO     0x00000036L
-#define GDC_CMD_1_VECTOR_NOEND_BLPO     0x00000037L
-#define GDC_CMD_AA_0_VECTOR             0x00000038L
-#define GDC_CMD_AA_1_VECTOR             0x00000039L
-#define GDC_CMD_AA_0_VECTOR_NOEND       0x0000003AL
-#define GDC_CMD_AA_1_VECTOR_NOEND       0x0000003BL
-#define GDC_CMD_AA_0_VECTOR_BLPO        0x0000003CL
-#define GDC_CMD_AA_1_VECTOR_BLPO        0x0000003DL
-#define GDC_CMD_AA_0_VECTOR_NOEND_BLPO  0x0000003EL
-#define GDC_CMD_AA_1_VECTOR_NOEND_BLPO  0x0000003FL
-
-#define GDC_CMD_BLT_FILL                0x00000041L
-#define GDC_CMD_BLT_DRAW                0x00000042L
-#define GDC_CMD_BITMAP                  0x00000043L
-#define GDC_CMD_BLTCOPY_TOP_LEFT        0x00000044L
-#define GDC_CMD_BLTCOPY_TOP_RIGHT       0x00000045L
-#define GDC_CMD_BLTCOPY_BOTTOM_LEFT     0x00000046L
-#define GDC_CMD_BLTCOPY_BOTTOM_RIGHT    0x00000047L
-#define GDC_CMD_LOAD_TEXTURE            0x00000048L
-#define GDC_CMD_LOAD_TILE               0x00000049L
-
-#define GDC_CMD_TRAP_RIGHT              0x00000060L
-#define GDC_CMD_TRAP_LEFT               0x00000061L
-#define GDC_CMD_TRIANGLE_FAN            0x00000062L
-#define GDC_CMD_FLAG_TRIANGLE_FAN       0x00000063L
-
-#define GDC_CMD_FLUSH_FB                0x000000C1L
-#define GDC_CMD_FLUSH_Z                 0x000000C2L
-
-#define GDC_CMD_POLYGON_BEGIN           0x000000E0L
-#define GDC_CMD_POLYGON_END             0x000000E1L
-#define GDC_CMD_CLEAR_POLY_FLAG         0x000000E2L
-#define GDC_CMD_NORMAL                  0x000000FFL
-
-#define GDC_CMD_VECTOR_BLPO_FLAG        0x00040000L
-#define GDC_CMD_FAST_VECTOR_BLPO_FLAG   0x00000004L
-
-/* for MB86293 or later */
-#define GDC_CMD_MDR1                            0x00000000L
-#define GDC_CMD_MDR1S                           0x00000002L
-#define GDC_CMD_MDR1B                           0x00000004L
-#define GDC_CMD_MDR2                            0x00000001L
-#define GDC_CMD_MDR2S                           0x00000003L
-#define GDC_CMD_MDR2TL                          0x00000007L
-#define GDC_CMD_GMDR1E                          0x00000010L
-#define GDC_CMD_GMDR2E                          0x00000020L
-#define GDC_CMD_OVERLAP_SHADOW_XY               0x00000000L
-#define GDC_CMD_OVERLAP_SHADOW_XY_COMPOSITION   0x00000001L
-#define GDC_CMD_OVERLAP_Z_PACKED_ONBS           0x00000007L
-#define GDC_CMD_OVERLAP_Z_ORIGIN                0x00000000L
-#define GDC_CMD_OVERLAP_Z_NON_TOPLEFT           0x00000001L
-#define GDC_CMD_OVERLAP_Z_BORDER                0x00000002L
-#define GDC_CMD_OVERLAP_Z_SHADOW                0x00000003L
-#define GDC_CMD_BLTCOPY_ALT_ALPHA               0x00000000L	/* Reserverd */
-#define GDC_CMD_DC_LOGOUT                       0x00000000L	/* Reserverd */
-#define GDC_CMD_BODY_FORE_COLOR                 0x00000000L
-#define GDC_CMD_BODY_BACK_COLOR                 0x00000001L
-#define GDC_CMD_SHADOW_FORE_COLOR               0x00000002L
-#define GDC_CMD_SHADOW_BACK_COLOR               0x00000003L
-#define GDC_CMD_BORDER_FORE_COLOR               0x00000004L
-#define GDC_CMD_BORDER_BACK_COLOR               0x00000005L
-
-/* Type Code Table */
-#define GDC_TYPE_G_NOP                                  0x00000020L
-#define GDC_TYPE_G_BEGIN                                0x00000021L
-#define GDC_TYPE_G_BEGINCONT                            0x00000022L
-#define GDC_TYPE_G_END                                  0x00000023L
-#define GDC_TYPE_G_VERTEX                               0x00000030L
-#define GDC_TYPE_G_VERTEXLOG                            0x00000032L
-#define GDC_TYPE_G_VERTEXNOPLOG                         0x00000033L
-#define GDC_TYPE_G_INIT                                 0x00000040L
-#define GDC_TYPE_G_VIEWPORT                             0x00000041L
-#define GDC_TYPE_G_DEPTHRANGE                           0x00000042L
-#define GDC_TYPE_G_LOADMATRIX                           0x00000043L
-#define GDC_TYPE_G_VIEWVOLUMEXYCLIP                     0x00000044L
-#define GDC_TYPE_G_VIEWVOLUMEZCLIP                      0x00000045L
-#define GDC_TYPE_G_VIEWVOLUMEWCLIP                      0x00000046L
-#define GDC_TYPE_SETLVERTEX2I                           0x00000072L
-#define GDC_TYPE_SETLVERTEX2IP                          0x00000073L
-#define GDC_TYPE_SETMODEREGISTER                        0x000000C0L
-#define GDC_TYPE_SETGMODEREGISTER                       0x000000C1L
-#define GDC_TYPE_OVERLAPXYOFFT                          0x000000C8L
-#define GDC_TYPE_OVERLAPZOFFT                           0x000000C9L
-#define GDC_TYPE_DC_LOGOUTADDR                          0x000000CCL
-#define GDC_TYPE_SETCOLORREGISTER                       0x000000CEL
-#define GDC_TYPE_G_BEGINE                               0x000000E1L
-#define GDC_TYPE_G_BEGINCONTE                           0x000000E2L
-#define GDC_TYPE_G_ENDE                                 0x000000E3L
-#define GDC_TYPE_DRAWPIXEL                              0x00000000L
-#define GDC_TYPE_DRAWPIXELZ                             0x00000001L
-#define GDC_TYPE_DRAWLINE                               0x00000002L
-#define GDC_TYPE_DRAWLINE2I                             0x00000003L
-#define GDC_TYPE_DRAWLINE2IP                            0x00000004L
-#define GDC_TYPE_DRAWTRAP                               0x00000005L
-#define GDC_TYPE_DRAWVERTEX2I                           0x00000006L
-#define GDC_TYPE_DRAWVERTEX2IP                          0x00000007L
-#define GDC_TYPE_DRAWRECTP                              0x00000009L
-#define GDC_TYPE_DRAWBITMAPP                            0x0000000BL
-#define GDC_TYPE_BLTCOPYP                               0x0000000DL
-#define GDC_TYPE_BLTCOPYALTERNATEP                      0x0000000FL
-#define GDC_TYPE_LOADTEXTUREP                           0x00000011L
-#define GDC_TYPE_BLTTEXTUREP                            0x00000013L
-#define GDC_TYPE_BLTCOPYALTALPHABLENDP                  0x0000001FL
-#define GDC_TYPE_SETVERTEX2I                            0x00000070L
-#define GDC_TYPE_SETVERTEX2IP                           0x00000071L
-#define GDC_TYPE_DRAW                                   0x000000F0L
-#define GDC_TYPE_SETREGISTER                            0x000000F1L
-#define GDC_TYPE_SYNC                                   0x000000FCL
-#define GDC_TYPE_INTERRUPT                              0x000000FDL
-#define GDC_TYPE_NOP                                    0x0
-
-/* Raster operation */
-#define GDC_ROP_CLEAR                   0x0000
-#define GDC_ROP_AND                     0x0001
-#define GDC_ROP_AND_REVERSE             0x0002
-#define GDC_ROP_COPY                    0x0003
-#define GDC_ROP_AND_INVERTED            0x0004
-#define GDC_ROP_NOP                     0x0005
-#define GDC_ROP_XOR                     0x0006
-#define GDC_ROP_OR                      0x0007
-#define GDC_ROP_NOR                     0x0008
-#define GDC_ROP_EQUIV                   0x0009
-#define GDC_ROP_INVERT                  0x000A
-#define GDC_ROP_OR_REVERSE              0x000B
-#define GDC_ROP_COPY_INVERTED           0x000C
-#define GDC_ROP_OR_INVERTED             0x000D
-#define GDC_ROP_NAND                    0x000E
-#define GDC_ROP_SET                     0x000F
-
-#endif
diff --git a/drivers/video/mb862xx/mb862xxfbdrv.c b/drivers/video/mb862xx/mb862xxfbdrv.c
deleted file mode 100644
index 0cd4c3318511..000000000000
--- a/drivers/video/mb862xx/mb862xxfbdrv.c
+++ /dev/null
@@ -1,1206 +0,0 @@
-/*
- * drivers/mb862xx/mb862xxfb.c
- *
- * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
- *
- * (C) 2008 Anatolij Gustschin <agust@denx.de>
- * DENX Software Engineering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#undef DEBUG
-
-#include <linux/fb.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#if defined(CONFIG_OF)
-#include <linux/of_platform.h>
-#endif
-#include "mb862xxfb.h"
-#include "mb862xx_reg.h"
-
-#define NR_PALETTE		256
-#define MB862XX_MEM_SIZE	0x1000000
-#define CORALP_MEM_SIZE		0x2000000
-#define CARMINE_MEM_SIZE	0x8000000
-#define DRV_NAME		"mb862xxfb"
-
-#if defined(CONFIG_SOCRATES)
-static struct mb862xx_gc_mode socrates_gc_mode = {
-	/* Mode for Prime View PM070WL4 TFT LCD Panel */
-	{ "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
-	/* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
-	16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
-};
-#endif
-
-/* Helpers */
-static inline int h_total(struct fb_var_screeninfo *var)
-{
-	return var->xres + var->left_margin +
-		var->right_margin + var->hsync_len;
-}
-
-static inline int v_total(struct fb_var_screeninfo *var)
-{
-	return var->yres + var->upper_margin +
-		var->lower_margin + var->vsync_len;
-}
-
-static inline int hsp(struct fb_var_screeninfo *var)
-{
-	return var->xres + var->right_margin - 1;
-}
-
-static inline int vsp(struct fb_var_screeninfo *var)
-{
-	return var->yres + var->lower_margin - 1;
-}
-
-static inline int d_pitch(struct fb_var_screeninfo *var)
-{
-	return var->xres * var->bits_per_pixel / 8;
-}
-
-static inline unsigned int chan_to_field(unsigned int chan,
-					 struct fb_bitfield *bf)
-{
-	chan &= 0xffff;
-	chan >>= 16 - bf->length;
-	return chan << bf->offset;
-}
-
-static int mb862xxfb_setcolreg(unsigned regno,
-			       unsigned red, unsigned green, unsigned blue,
-			       unsigned transp, struct fb_info *info)
-{
-	struct mb862xxfb_par *par = info->par;
-	unsigned int val;
-
-	switch (info->fix.visual) {
-	case FB_VISUAL_TRUECOLOR:
-		if (regno < 16) {
-			val  = chan_to_field(red,   &info->var.red);
-			val |= chan_to_field(green, &info->var.green);
-			val |= chan_to_field(blue,  &info->var.blue);
-			par->pseudo_palette[regno] = val;
-		}
-		break;
-	case FB_VISUAL_PSEUDOCOLOR:
-		if (regno < 256) {
-			val = (red >> 8) << 16;
-			val |= (green >> 8) << 8;
-			val |= blue >> 8;
-			outreg(disp, GC_L0PAL0 + (regno * 4), val);
-		}
-		break;
-	default:
-		return 1;   /* unsupported type */
-	}
-	return 0;
-}
-
-static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
-			       struct fb_info *fbi)
-{
-	unsigned long tmp;
-
-	if (fbi->dev)
-		dev_dbg(fbi->dev, "%s\n", __func__);
-
-	/* check if these values fit into the registers */
-	if (var->hsync_len > 255 || var->vsync_len > 255)
-		return -EINVAL;
-
-	if ((var->xres + var->right_margin) >= 4096)
-		return -EINVAL;
-
-	if ((var->yres + var->lower_margin) > 4096)
-		return -EINVAL;
-
-	if (h_total(var) > 4096 || v_total(var) > 4096)
-		return -EINVAL;
-
-	if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
-		return -EINVAL;
-
-	if (var->bits_per_pixel <= 8)
-		var->bits_per_pixel = 8;
-	else if (var->bits_per_pixel <= 16)
-		var->bits_per_pixel = 16;
-	else if (var->bits_per_pixel <= 32)
-		var->bits_per_pixel = 32;
-
-	/*
-	 * can cope with 8,16 or 24/32bpp if resulting
-	 * pitch is divisible by 64 without remainder
-	 */
-	if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
-		int r;
-
-		var->bits_per_pixel = 0;
-		do {
-			var->bits_per_pixel += 8;
-			r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
-		} while (r && var->bits_per_pixel <= 32);
-
-		if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
-			return -EINVAL;
-	}
-
-	/* line length is going to be 128 bit aligned */
-	tmp = (var->xres * var->bits_per_pixel) / 8;
-	if ((tmp & 15) != 0)
-		return -EINVAL;
-
-	/* set r/g/b positions and validate bpp */
-	switch (var->bits_per_pixel) {
-	case 8:
-		var->red.length		= var->bits_per_pixel;
-		var->green.length	= var->bits_per_pixel;
-		var->blue.length	= var->bits_per_pixel;
-		var->red.offset		= 0;
-		var->green.offset	= 0;
-		var->blue.offset	= 0;
-		var->transp.length	= 0;
-		break;
-	case 16:
-		var->red.length		= 5;
-		var->green.length	= 5;
-		var->blue.length	= 5;
-		var->red.offset		= 10;
-		var->green.offset	= 5;
-		var->blue.offset	= 0;
-		var->transp.length	= 0;
-		break;
-	case 24:
-	case 32:
-		var->transp.length	= 8;
-		var->red.length		= 8;
-		var->green.length	= 8;
-		var->blue.length	= 8;
-		var->transp.offset	= 24;
-		var->red.offset		= 16;
-		var->green.offset	= 8;
-		var->blue.offset	= 0;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-/*
- * set display parameters
- */
-static int mb862xxfb_set_par(struct fb_info *fbi)
-{
-	struct mb862xxfb_par *par = fbi->par;
-	unsigned long reg, sc;
-
-	dev_dbg(par->dev, "%s\n", __func__);
-	if (par->type == BT_CORALP)
-		mb862xxfb_init_accel(fbi, fbi->var.xres);
-
-	if (par->pre_init)
-		return 0;
-
-	/* disp off */
-	reg = inreg(disp, GC_DCM1);
-	reg &= ~GC_DCM01_DEN;
-	outreg(disp, GC_DCM1, reg);
-
-	/* set display reference clock div. */
-	sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
-	reg = inreg(disp, GC_DCM1);
-	reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
-	reg |= sc << 8;
-	outreg(disp, GC_DCM1, reg);
-	dev_dbg(par->dev, "SC 0x%lx\n", sc);
-
-	/* disp dimension, format */
-	reg =  pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
-		    (fbi->var.yres - 1));
-	if (fbi->var.bits_per_pixel == 16)
-		reg |= GC_L0M_L0C_16;
-	outreg(disp, GC_L0M, reg);
-
-	if (fbi->var.bits_per_pixel == 32) {
-		reg = inreg(disp, GC_L0EM);
-		outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
-	}
-	outreg(disp, GC_WY_WX, 0);
-	reg = pack(fbi->var.yres - 1, fbi->var.xres);
-	outreg(disp, GC_WH_WW, reg);
-	outreg(disp, GC_L0OA0, 0);
-	outreg(disp, GC_L0DA0, 0);
-	outreg(disp, GC_L0DY_L0DX, 0);
-	outreg(disp, GC_L0WY_L0WX, 0);
-	outreg(disp, GC_L0WH_L0WW, reg);
-
-	/* both HW-cursors off */
-	reg = inreg(disp, GC_CPM_CUTC);
-	reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
-	outreg(disp, GC_CPM_CUTC, reg);
-
-	/* timings */
-	reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
-	outreg(disp, GC_HDB_HDP, reg);
-	reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
-	outreg(disp, GC_VDP_VSP, reg);
-	reg = ((fbi->var.vsync_len - 1) << 24) |
-	      pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
-	outreg(disp, GC_VSW_HSW_HSP, reg);
-	outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
-	outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
-
-	/* display on */
-	reg = inreg(disp, GC_DCM1);
-	reg |= GC_DCM01_DEN | GC_DCM01_L0E;
-	reg &= ~GC_DCM01_ESY;
-	outreg(disp, GC_DCM1, reg);
-	return 0;
-}
-
-static int mb862xxfb_pan(struct fb_var_screeninfo *var,
-			 struct fb_info *info)
-{
-	struct mb862xxfb_par *par = info->par;
-	unsigned long reg;
-
-	reg = pack(var->yoffset, var->xoffset);
-	outreg(disp, GC_L0WY_L0WX, reg);
-
-	reg = pack(info->var.yres_virtual, info->var.xres_virtual);
-	outreg(disp, GC_L0WH_L0WW, reg);
-	return 0;
-}
-
-static int mb862xxfb_blank(int mode, struct fb_info *fbi)
-{
-	struct mb862xxfb_par  *par = fbi->par;
-	unsigned long reg;
-
-	dev_dbg(fbi->dev, "blank mode=%d\n", mode);
-
-	switch (mode) {
-	case FB_BLANK_POWERDOWN:
-		reg = inreg(disp, GC_DCM1);
-		reg &= ~GC_DCM01_DEN;
-		outreg(disp, GC_DCM1, reg);
-		break;
-	case FB_BLANK_UNBLANK:
-		reg = inreg(disp, GC_DCM1);
-		reg |= GC_DCM01_DEN;
-		outreg(disp, GC_DCM1, reg);
-		break;
-	case FB_BLANK_NORMAL:
-	case FB_BLANK_VSYNC_SUSPEND:
-	case FB_BLANK_HSYNC_SUSPEND:
-	default:
-		return 1;
-	}
-	return 0;
-}
-
-static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
-			   unsigned long arg)
-{
-	struct mb862xxfb_par *par = fbi->par;
-	struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
-	void __user *argp = (void __user *)arg;
-	int *enable;
-	u32 l1em = 0;
-
-	switch (cmd) {
-	case MB862XX_L1_GET_CFG:
-		if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
-			return -EFAULT;
-		break;
-	case MB862XX_L1_SET_CFG:
-		if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
-			return -EFAULT;
-		if (l1_cfg->dh == 0 || l1_cfg->dw == 0)
-			return -EINVAL;
-		if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
-			/* downscaling */
-			outreg(cap, GC_CAP_CSC,
-				pack((l1_cfg->sh << 11) / l1_cfg->dh,
-				     (l1_cfg->sw << 11) / l1_cfg->dw));
-			l1em = inreg(disp, GC_L1EM);
-			l1em &= ~GC_L1EM_DM;
-		} else if ((l1_cfg->sw <= l1_cfg->dw) &&
-			   (l1_cfg->sh <= l1_cfg->dh)) {
-			/* upscaling */
-			outreg(cap, GC_CAP_CSC,
-				pack((l1_cfg->sh << 11) / l1_cfg->dh,
-				     (l1_cfg->sw << 11) / l1_cfg->dw));
-			outreg(cap, GC_CAP_CMSS,
-				pack(l1_cfg->sw >> 1, l1_cfg->sh));
-			outreg(cap, GC_CAP_CMDS,
-				pack(l1_cfg->dw >> 1, l1_cfg->dh));
-			l1em = inreg(disp, GC_L1EM);
-			l1em |= GC_L1EM_DM;
-		}
-
-		if (l1_cfg->mirror) {
-			outreg(cap, GC_CAP_CBM,
-				inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
-			l1em |= l1_cfg->dw * 2 - 8;
-		} else {
-			outreg(cap, GC_CAP_CBM,
-				inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
-			l1em &= 0xffff0000;
-		}
-		outreg(disp, GC_L1EM, l1em);
-		break;
-	case MB862XX_L1_ENABLE:
-		enable = (int *)arg;
-		if (*enable) {
-			outreg(disp, GC_L1DA, par->cap_buf);
-			outreg(cap, GC_CAP_IMG_START,
-				pack(l1_cfg->sy >> 1, l1_cfg->sx));
-			outreg(cap, GC_CAP_IMG_END,
-				pack(l1_cfg->sh, l1_cfg->sw));
-			outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
-					     (par->l1_stride << 16));
-			outreg(disp, GC_L1WY_L1WX,
-				pack(l1_cfg->dy, l1_cfg->dx));
-			outreg(disp, GC_L1WH_L1WW,
-				pack(l1_cfg->dh - 1, l1_cfg->dw));
-			outreg(disp, GC_DLS, 1);
-			outreg(cap, GC_CAP_VCM,
-				GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
-			outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
-					      GC_DCM1_DEN | GC_DCM1_L1E);
-		} else {
-			outreg(cap, GC_CAP_VCM,
-				inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
-			outreg(disp, GC_DCM1,
-				inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
-		}
-		break;
-	case MB862XX_L1_CAP_CTL:
-		enable = (int *)arg;
-		if (*enable) {
-			outreg(cap, GC_CAP_VCM,
-				inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
-		} else {
-			outreg(cap, GC_CAP_VCM,
-				inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
-		}
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-/* framebuffer ops */
-static struct fb_ops mb862xxfb_ops = {
-	.owner		= THIS_MODULE,
-	.fb_check_var	= mb862xxfb_check_var,
-	.fb_set_par	= mb862xxfb_set_par,
-	.fb_setcolreg	= mb862xxfb_setcolreg,
-	.fb_blank	= mb862xxfb_blank,
-	.fb_pan_display	= mb862xxfb_pan,
-	.fb_fillrect	= cfb_fillrect,
-	.fb_copyarea	= cfb_copyarea,
-	.fb_imageblit	= cfb_imageblit,
-	.fb_ioctl	= mb862xxfb_ioctl,
-};
-
-/* initialize fb_info data */
-static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
-{
-	struct mb862xxfb_par *par = fbi->par;
-	struct mb862xx_gc_mode *mode = par->gc_mode;
-	unsigned long reg;
-	int stride;
-
-	fbi->fbops = &mb862xxfb_ops;
-	fbi->pseudo_palette = par->pseudo_palette;
-	fbi->screen_base = par->fb_base;
-	fbi->screen_size = par->mapped_vram;
-
-	strcpy(fbi->fix.id, DRV_NAME);
-	fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
-	fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
-	fbi->fix.mmio_len = par->mmio_len;
-	fbi->fix.accel = FB_ACCEL_NONE;
-	fbi->fix.type = FB_TYPE_PACKED_PIXELS;
-	fbi->fix.type_aux = 0;
-	fbi->fix.xpanstep = 1;
-	fbi->fix.ypanstep = 1;
-	fbi->fix.ywrapstep = 0;
-
-	reg = inreg(disp, GC_DCM1);
-	if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
-		/* get the disp mode from active display cfg */
-		unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
-		unsigned long hsp, vsp, ht, vt;
-
-		dev_dbg(par->dev, "using bootloader's disp. mode\n");
-		fbi->var.pixclock = (sc * 1000000) / par->refclk;
-		fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
-		reg = inreg(disp, GC_VDP_VSP);
-		fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
-		vsp = (reg & 0x0fff) + 1;
-		fbi->var.xres_virtual = fbi->var.xres;
-		fbi->var.yres_virtual = fbi->var.yres;
-		reg = inreg(disp, GC_L0EM);
-		if (reg & GC_L0EM_L0EC_24) {
-			fbi->var.bits_per_pixel = 32;
-		} else {
-			reg = inreg(disp, GC_L0M);
-			if (reg & GC_L0M_L0C_16)
-				fbi->var.bits_per_pixel = 16;
-			else
-				fbi->var.bits_per_pixel = 8;
-		}
-		reg = inreg(disp, GC_VSW_HSW_HSP);
-		fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
-		fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
-		hsp = (reg & 0xffff) + 1;
-		ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
-		fbi->var.right_margin = hsp - fbi->var.xres;
-		fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
-		vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
-		fbi->var.lower_margin = vsp - fbi->var.yres;
-		fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
-	} else if (mode) {
-		dev_dbg(par->dev, "using supplied mode\n");
-		fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
-		fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
-	} else {
-		int ret;
-
-		ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
-				   NULL, 0, NULL, 16);
-		if (ret == 0 || ret == 4) {
-			dev_err(par->dev,
-				"failed to get initial mode\n");
-			return -EINVAL;
-		}
-	}
-
-	fbi->var.xoffset = 0;
-	fbi->var.yoffset = 0;
-	fbi->var.grayscale = 0;
-	fbi->var.nonstd = 0;
-	fbi->var.height = -1;
-	fbi->var.width = -1;
-	fbi->var.accel_flags = 0;
-	fbi->var.vmode = FB_VMODE_NONINTERLACED;
-	fbi->var.activate = FB_ACTIVATE_NOW;
-	fbi->flags = FBINFO_DEFAULT |
-#ifdef __BIG_ENDIAN
-		     FBINFO_FOREIGN_ENDIAN |
-#endif
-		     FBINFO_HWACCEL_XPAN |
-		     FBINFO_HWACCEL_YPAN;
-
-	/* check and possibly fix bpp */
-	if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
-		dev_err(par->dev, "check_var() failed on initial setup?\n");
-
-	fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
-			 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
-	fbi->fix.line_length = (fbi->var.xres_virtual *
-				fbi->var.bits_per_pixel) / 8;
-	fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
-
-	/*
-	 * reserve space for capture buffers and two cursors
-	 * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
-	 */
-	par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
-	par->cap_len = 0x1bd800;
-	par->l1_cfg.sx = 0;
-	par->l1_cfg.sy = 0;
-	par->l1_cfg.sw = 720;
-	par->l1_cfg.sh = 576;
-	par->l1_cfg.dx = 0;
-	par->l1_cfg.dy = 0;
-	par->l1_cfg.dw = 720;
-	par->l1_cfg.dh = 576;
-	stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
-	par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
-	outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
-				(par->l1_stride << 16));
-	outreg(cap, GC_CAP_CBOA, par->cap_buf);
-	outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
-	return 0;
-}
-
-/*
- * show some display controller and cursor registers
- */
-static ssize_t mb862xxfb_show_dispregs(struct device *dev,
-				       struct device_attribute *attr, char *buf)
-{
-	struct fb_info *fbi = dev_get_drvdata(dev);
-	struct mb862xxfb_par *par = fbi->par;
-	char *ptr = buf;
-	unsigned int reg;
-
-	for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
-		ptr += sprintf(ptr, "%08x = %08x\n",
-			       reg, inreg(disp, reg));
-
-	for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
-		ptr += sprintf(ptr, "%08x = %08x\n",
-			       reg, inreg(disp, reg));
-
-	for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
-		ptr += sprintf(ptr, "%08x = %08x\n",
-			       reg, inreg(disp, reg));
-
-	for (reg = 0x400; reg <= 0x410; reg += 4)
-		ptr += sprintf(ptr, "geo %08x = %08x\n",
-			       reg, inreg(geo, reg));
-
-	for (reg = 0x400; reg <= 0x410; reg += 4)
-		ptr += sprintf(ptr, "draw %08x = %08x\n",
-			       reg, inreg(draw, reg));
-
-	for (reg = 0x440; reg <= 0x450; reg += 4)
-		ptr += sprintf(ptr, "draw %08x = %08x\n",
-			       reg, inreg(draw, reg));
-
-	return ptr - buf;
-}
-
-static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
-
-static irqreturn_t mb862xx_intr(int irq, void *dev_id)
-{
-	struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
-	unsigned long reg_ist, mask;
-
-	if (!par)
-		return IRQ_NONE;
-
-	if (par->type == BT_CARMINE) {
-		/* Get Interrupt Status */
-		reg_ist = inreg(ctrl, GC_CTRL_STATUS);
-		mask = inreg(ctrl, GC_CTRL_INT_MASK);
-		if (reg_ist == 0)
-			return IRQ_HANDLED;
-
-		reg_ist &= mask;
-		if (reg_ist == 0)
-			return IRQ_HANDLED;
-
-		/* Clear interrupt status */
-		outreg(ctrl, 0x0, reg_ist);
-	} else {
-		/* Get status */
-		reg_ist = inreg(host, GC_IST);
-		mask = inreg(host, GC_IMASK);
-
-		reg_ist &= mask;
-		if (reg_ist == 0)
-			return IRQ_HANDLED;
-
-		/* Clear status */
-		outreg(host, GC_IST, ~reg_ist);
-	}
-	return IRQ_HANDLED;
-}
-
-#if defined(CONFIG_FB_MB862XX_LIME)
-/*
- * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
- */
-static int mb862xx_gdc_init(struct mb862xxfb_par *par)
-{
-	unsigned long ccf, mmr;
-	unsigned long ver, rev;
-
-	if (!par)
-		return -ENODEV;
-
-#if defined(CONFIG_FB_PRE_INIT_FB)
-	par->pre_init = 1;
-#endif
-	par->host = par->mmio_base;
-	par->i2c = par->mmio_base + MB862XX_I2C_BASE;
-	par->disp = par->mmio_base + MB862XX_DISP_BASE;
-	par->cap = par->mmio_base + MB862XX_CAP_BASE;
-	par->draw = par->mmio_base + MB862XX_DRAW_BASE;
-	par->geo = par->mmio_base + MB862XX_GEO_BASE;
-	par->pio = par->mmio_base + MB862XX_PIO_BASE;
-
-	par->refclk = GC_DISP_REFCLK_400;
-
-	ver = inreg(host, GC_CID);
-	rev = inreg(pio, GC_REVISION);
-	if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
-		dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
-			 (int)rev & 0xff);
-		par->type = BT_LIME;
-		ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
-		mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
-	} else {
-		dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
-		return -ENODEV;
-	}
-
-	if (!par->pre_init) {
-		outreg(host, GC_CCF, ccf);
-		udelay(200);
-		outreg(host, GC_MMR, mmr);
-		udelay(10);
-	}
-
-	/* interrupt status */
-	outreg(host, GC_IST, 0);
-	outreg(host, GC_IMASK, GC_INT_EN);
-	return 0;
-}
-
-static int of_platform_mb862xx_probe(struct platform_device *ofdev)
-{
-	struct device_node *np = ofdev->dev.of_node;
-	struct device *dev = &ofdev->dev;
-	struct mb862xxfb_par *par;
-	struct fb_info *info;
-	struct resource res;
-	resource_size_t res_size;
-	unsigned long ret = -ENODEV;
-
-	if (of_address_to_resource(np, 0, &res)) {
-		dev_err(dev, "Invalid address\n");
-		return -ENXIO;
-	}
-
-	info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
-	if (info == NULL) {
-		dev_err(dev, "cannot allocate framebuffer\n");
-		return -ENOMEM;
-	}
-
-	par = info->par;
-	par->info = info;
-	par->dev = dev;
-
-	par->irq = irq_of_parse_and_map(np, 0);
-	if (par->irq == NO_IRQ) {
-		dev_err(dev, "failed to map irq\n");
-		ret = -ENODEV;
-		goto fbrel;
-	}
-
-	res_size = resource_size(&res);
-	par->res = request_mem_region(res.start, res_size, DRV_NAME);
-	if (par->res == NULL) {
-		dev_err(dev, "Cannot claim framebuffer/mmio\n");
-		ret = -ENXIO;
-		goto irqdisp;
-	}
-
-#if defined(CONFIG_SOCRATES)
-	par->gc_mode = &socrates_gc_mode;
-#endif
-
-	par->fb_base_phys = res.start;
-	par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
-	par->mmio_len = MB862XX_MMIO_SIZE;
-	if (par->gc_mode)
-		par->mapped_vram = par->gc_mode->max_vram;
-	else
-		par->mapped_vram = MB862XX_MEM_SIZE;
-
-	par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
-	if (par->fb_base == NULL) {
-		dev_err(dev, "Cannot map framebuffer\n");
-		goto rel_reg;
-	}
-
-	par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
-	if (par->mmio_base == NULL) {
-		dev_err(dev, "Cannot map registers\n");
-		goto fb_unmap;
-	}
-
-	dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
-		(u64)par->fb_base_phys, (ulong)par->mapped_vram);
-	dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
-		(u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
-
-	if (mb862xx_gdc_init(par))
-		goto io_unmap;
-
-	if (request_irq(par->irq, mb862xx_intr, 0,
-			DRV_NAME, (void *)par)) {
-		dev_err(dev, "Cannot request irq\n");
-		goto io_unmap;
-	}
-
-	mb862xxfb_init_fbinfo(info);
-
-	if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
-		dev_err(dev, "Could not allocate cmap for fb_info.\n");
-		goto free_irq;
-	}
-
-	if ((info->fbops->fb_set_par)(info))
-		dev_err(dev, "set_var() failed on initial setup?\n");
-
-	if (register_framebuffer(info)) {
-		dev_err(dev, "failed to register framebuffer\n");
-		goto rel_cmap;
-	}
-
-	dev_set_drvdata(dev, info);
-
-	if (device_create_file(dev, &dev_attr_dispregs))
-		dev_err(dev, "Can't create sysfs regdump file\n");
-	return 0;
-
-rel_cmap:
-	fb_dealloc_cmap(&info->cmap);
-free_irq:
-	outreg(host, GC_IMASK, 0);
-	free_irq(par->irq, (void *)par);
-io_unmap:
-	iounmap(par->mmio_base);
-fb_unmap:
-	iounmap(par->fb_base);
-rel_reg:
-	release_mem_region(res.start, res_size);
-irqdisp:
-	irq_dispose_mapping(par->irq);
-fbrel:
-	framebuffer_release(info);
-	return ret;
-}
-
-static int of_platform_mb862xx_remove(struct platform_device *ofdev)
-{
-	struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
-	struct mb862xxfb_par *par = fbi->par;
-	resource_size_t res_size = resource_size(par->res);
-	unsigned long reg;
-
-	dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
-
-	/* display off */
-	reg = inreg(disp, GC_DCM1);
-	reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
-	outreg(disp, GC_DCM1, reg);
-
-	/* disable interrupts */
-	outreg(host, GC_IMASK, 0);
-
-	free_irq(par->irq, (void *)par);
-	irq_dispose_mapping(par->irq);
-
-	device_remove_file(&ofdev->dev, &dev_attr_dispregs);
-
-	unregister_framebuffer(fbi);
-	fb_dealloc_cmap(&fbi->cmap);
-
-	iounmap(par->mmio_base);
-	iounmap(par->fb_base);
-
-	release_mem_region(par->res->start, res_size);
-	framebuffer_release(fbi);
-	return 0;
-}
-
-/*
- * common types
- */
-static struct of_device_id of_platform_mb862xx_tbl[] = {
-	{ .compatible = "fujitsu,MB86276", },
-	{ .compatible = "fujitsu,lime", },
-	{ .compatible = "fujitsu,MB86277", },
-	{ .compatible = "fujitsu,mint", },
-	{ .compatible = "fujitsu,MB86293", },
-	{ .compatible = "fujitsu,MB86294", },
-	{ .compatible = "fujitsu,coral", },
-	{ /* end */ }
-};
-
-static struct platform_driver of_platform_mb862xxfb_driver = {
-	.driver = {
-		.name = DRV_NAME,
-		.owner = THIS_MODULE,
-		.of_match_table = of_platform_mb862xx_tbl,
-	},
-	.probe		= of_platform_mb862xx_probe,
-	.remove		= of_platform_mb862xx_remove,
-};
-#endif
-
-#if defined(CONFIG_FB_MB862XX_PCI_GDC)
-static int coralp_init(struct mb862xxfb_par *par)
-{
-	int cn, ver;
-
-	par->host = par->mmio_base;
-	par->i2c = par->mmio_base + MB862XX_I2C_BASE;
-	par->disp = par->mmio_base + MB862XX_DISP_BASE;
-	par->cap = par->mmio_base + MB862XX_CAP_BASE;
-	par->draw = par->mmio_base + MB862XX_DRAW_BASE;
-	par->geo = par->mmio_base + MB862XX_GEO_BASE;
-	par->pio = par->mmio_base + MB862XX_PIO_BASE;
-
-	par->refclk = GC_DISP_REFCLK_400;
-
-	if (par->mapped_vram >= 0x2000000) {
-		/* relocate gdc registers space */
-		writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
-		udelay(1); /* wait at least 20 bus cycles */
-	}
-
-	ver = inreg(host, GC_CID);
-	cn = (ver & GC_CID_CNAME_MSK) >> 8;
-	ver = ver & GC_CID_VERSION_MSK;
-	if (cn == 3) {
-		unsigned long reg;
-
-		dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
-			 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
-			 par->pdev->revision);
-		reg = inreg(disp, GC_DCM1);
-		if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
-			par->pre_init = 1;
-
-		if (!par->pre_init) {
-			outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
-			udelay(200);
-			outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
-			udelay(10);
-		}
-		/* Clear interrupt status */
-		outreg(host, GC_IST, 0);
-	} else {
-		return -ENODEV;
-	}
-
-	mb862xx_i2c_init(par);
-	return 0;
-}
-
-static int init_dram_ctrl(struct mb862xxfb_par *par)
-{
-	unsigned long i = 0;
-
-	/*
-	 * Set io mode first! Spec. says IC may be destroyed
-	 * if not set to SSTL2/LVCMOS before init.
-	 */
-	outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
-
-	/* DRAM init */
-	outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
-	outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
-	outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
-	       GC_EVB_DCTL_REFRESH_SETTIME2);
-	outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
-	outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
-	outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
-
-	/* DLL reset done? */
-	while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
-		udelay(GC_DCTL_INIT_WAIT_INTERVAL);
-		if (i++ > GC_DCTL_INIT_WAIT_CNT) {
-			dev_err(par->dev, "VRAM init failed.\n");
-			return -EINVAL;
-		}
-	}
-	outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
-	outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
-	return 0;
-}
-
-static int carmine_init(struct mb862xxfb_par *par)
-{
-	unsigned long reg;
-
-	par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
-	par->i2c = par->mmio_base + MB86297_I2C_BASE;
-	par->disp = par->mmio_base + MB86297_DISP0_BASE;
-	par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
-	par->cap = par->mmio_base + MB86297_CAP0_BASE;
-	par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
-	par->draw = par->mmio_base + MB86297_DRAW_BASE;
-	par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
-	par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
-
-	par->refclk = GC_DISP_REFCLK_533;
-
-	/* warm up */
-	reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
-	outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
-
-	/* check for engine module revision */
-	if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
-		dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
-			 par->pdev->revision);
-	else
-		goto err_init;
-
-	reg &= ~GC_CTRL_CLK_EN_2D3D;
-	outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
-
-	/* set up vram */
-	if (init_dram_ctrl(par) < 0)
-		goto err_init;
-
-	outreg(ctrl, GC_CTRL_INT_MASK, 0);
-	return 0;
-
-err_init:
-	outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
-	return -EINVAL;
-}
-
-static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
-{
-	switch (par->type) {
-	case BT_CORALP:
-		return coralp_init(par);
-	case BT_CARMINE:
-		return carmine_init(par);
-	default:
-		return -ENODEV;
-	}
-}
-
-#define CHIP_ID(id)	\
-	{ PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
-
-static struct pci_device_id mb862xx_pci_tbl[] = {
-	/* MB86295/MB86296 */
-	CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
-	CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
-	/* MB86297 */
-	CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
-	{ 0, }
-};
-
-MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
-
-static int mb862xx_pci_probe(struct pci_dev *pdev,
-			     const struct pci_device_id *ent)
-{
-	struct mb862xxfb_par *par;
-	struct fb_info *info;
-	struct device *dev = &pdev->dev;
-	int ret;
-
-	ret = pci_enable_device(pdev);
-	if (ret < 0) {
-		dev_err(dev, "Cannot enable PCI device\n");
-		goto out;
-	}
-
-	info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
-	if (!info) {
-		dev_err(dev, "framebuffer alloc failed\n");
-		ret = -ENOMEM;
-		goto dis_dev;
-	}
-
-	par = info->par;
-	par->info = info;
-	par->dev = dev;
-	par->pdev = pdev;
-	par->irq = pdev->irq;
-
-	ret = pci_request_regions(pdev, DRV_NAME);
-	if (ret < 0) {
-		dev_err(dev, "Cannot reserve region(s) for PCI device\n");
-		goto rel_fb;
-	}
-
-	switch (pdev->device) {
-	case PCI_DEVICE_ID_FUJITSU_CORALP:
-	case PCI_DEVICE_ID_FUJITSU_CORALPA:
-		par->fb_base_phys = pci_resource_start(par->pdev, 0);
-		par->mapped_vram = CORALP_MEM_SIZE;
-		if (par->mapped_vram >= 0x2000000) {
-			par->mmio_base_phys = par->fb_base_phys +
-					      MB862XX_MMIO_HIGH_BASE;
-		} else {
-			par->mmio_base_phys = par->fb_base_phys +
-					      MB862XX_MMIO_BASE;
-		}
-		par->mmio_len = MB862XX_MMIO_SIZE;
-		par->type = BT_CORALP;
-		break;
-	case PCI_DEVICE_ID_FUJITSU_CARMINE:
-		par->fb_base_phys = pci_resource_start(par->pdev, 2);
-		par->mmio_base_phys = pci_resource_start(par->pdev, 3);
-		par->mmio_len = pci_resource_len(par->pdev, 3);
-		par->mapped_vram = CARMINE_MEM_SIZE;
-		par->type = BT_CARMINE;
-		break;
-	default:
-		/* should never occur */
-		ret = -EIO;
-		goto rel_reg;
-	}
-
-	par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
-	if (par->fb_base == NULL) {
-		dev_err(dev, "Cannot map framebuffer\n");
-		ret = -EIO;
-		goto rel_reg;
-	}
-
-	par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
-	if (par->mmio_base == NULL) {
-		dev_err(dev, "Cannot map registers\n");
-		ret = -EIO;
-		goto fb_unmap;
-	}
-
-	dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
-		(unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
-	dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
-		(unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
-
-	ret = mb862xx_pci_gdc_init(par);
-	if (ret)
-		goto io_unmap;
-
-	ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
-			  DRV_NAME, (void *)par);
-	if (ret) {
-		dev_err(dev, "Cannot request irq\n");
-		goto io_unmap;
-	}
-
-	mb862xxfb_init_fbinfo(info);
-
-	if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
-		dev_err(dev, "Could not allocate cmap for fb_info.\n");
-		ret = -ENOMEM;
-		goto free_irq;
-	}
-
-	if ((info->fbops->fb_set_par)(info))
-		dev_err(dev, "set_var() failed on initial setup?\n");
-
-	ret = register_framebuffer(info);
-	if (ret < 0) {
-		dev_err(dev, "failed to register framebuffer\n");
-		goto rel_cmap;
-	}
-
-	pci_set_drvdata(pdev, info);
-
-	if (device_create_file(dev, &dev_attr_dispregs))
-		dev_err(dev, "Can't create sysfs regdump file\n");
-
-	if (par->type == BT_CARMINE)
-		outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
-	else
-		outreg(host, GC_IMASK, GC_INT_EN);
-
-	return 0;
-
-rel_cmap:
-	fb_dealloc_cmap(&info->cmap);
-free_irq:
-	free_irq(par->irq, (void *)par);
-io_unmap:
-	iounmap(par->mmio_base);
-fb_unmap:
-	iounmap(par->fb_base);
-rel_reg:
-	pci_release_regions(pdev);
-rel_fb:
-	framebuffer_release(info);
-dis_dev:
-	pci_disable_device(pdev);
-out:
-	return ret;
-}
-
-static void mb862xx_pci_remove(struct pci_dev *pdev)
-{
-	struct fb_info *fbi = pci_get_drvdata(pdev);
-	struct mb862xxfb_par *par = fbi->par;
-	unsigned long reg;
-
-	dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
-
-	/* display off */
-	reg = inreg(disp, GC_DCM1);
-	reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
-	outreg(disp, GC_DCM1, reg);
-
-	if (par->type == BT_CARMINE) {
-		outreg(ctrl, GC_CTRL_INT_MASK, 0);
-		outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
-	} else {
-		outreg(host, GC_IMASK, 0);
-	}
-
-	mb862xx_i2c_exit(par);
-
-	device_remove_file(&pdev->dev, &dev_attr_dispregs);
-
-	unregister_framebuffer(fbi);
-	fb_dealloc_cmap(&fbi->cmap);
-
-	free_irq(par->irq, (void *)par);
-	iounmap(par->mmio_base);
-	iounmap(par->fb_base);
-
-	pci_release_regions(pdev);
-	framebuffer_release(fbi);
-	pci_disable_device(pdev);
-}
-
-static struct pci_driver mb862xxfb_pci_driver = {
-	.name		= DRV_NAME,
-	.id_table	= mb862xx_pci_tbl,
-	.probe		= mb862xx_pci_probe,
-	.remove		= mb862xx_pci_remove,
-};
-#endif
-
-static int mb862xxfb_init(void)
-{
-	int ret = -ENODEV;
-
-#if defined(CONFIG_FB_MB862XX_LIME)
-	ret = platform_driver_register(&of_platform_mb862xxfb_driver);
-#endif
-#if defined(CONFIG_FB_MB862XX_PCI_GDC)
-	ret = pci_register_driver(&mb862xxfb_pci_driver);
-#endif
-	return ret;
-}
-
-static void __exit mb862xxfb_exit(void)
-{
-#if defined(CONFIG_FB_MB862XX_LIME)
-	platform_driver_unregister(&of_platform_mb862xxfb_driver);
-#endif
-#if defined(CONFIG_FB_MB862XX_PCI_GDC)
-	pci_unregister_driver(&mb862xxfb_pci_driver);
-#endif
-}
-
-module_init(mb862xxfb_init);
-module_exit(mb862xxfb_exit);
-
-MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
-MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
-MODULE_LICENSE("GPL v2");