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author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2014-06-08 10:24:07 +0400 |
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committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2014-06-08 10:24:07 +0400 |
commit | a292241cccb7e20e8b997a9a44177e7c98141859 (patch) | |
tree | a0b0bb95e7dce3233a2d8b203f9e326cdec7a00e /drivers/video/fbdev/riva/rivafb.h | |
parent | d49cb7aeebb974713f9f7ab2991352d3050b095b (diff) | |
parent | 68807a0c2015cb40df4869e16651f0ce5cc14d52 (diff) | |
download | linux-a292241cccb7e20e8b997a9a44177e7c98141859.tar.xz |
Merge branch 'next' into for-linus
Prepare input updates for 3.16.
Diffstat (limited to 'drivers/video/fbdev/riva/rivafb.h')
-rw-r--r-- | drivers/video/fbdev/riva/rivafb.h | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/drivers/video/fbdev/riva/rivafb.h b/drivers/video/fbdev/riva/rivafb.h new file mode 100644 index 000000000000..d9f107b704c6 --- /dev/null +++ b/drivers/video/fbdev/riva/rivafb.h @@ -0,0 +1,77 @@ +#ifndef __RIVAFB_H +#define __RIVAFB_H + +#include <linux/fb.h> +#include <video/vga.h> +#include <linux/i2c.h> +#include <linux/i2c-algo-bit.h> + +#include "riva_hw.h" + +/* GGI compatibility macros */ +#define NUM_SEQ_REGS 0x05 +#define NUM_CRT_REGS 0x41 +#define NUM_GRC_REGS 0x09 +#define NUM_ATC_REGS 0x15 + +/* I2C */ +#define DDC_SCL_READ_MASK (1 << 2) +#define DDC_SCL_WRITE_MASK (1 << 5) +#define DDC_SDA_READ_MASK (1 << 3) +#define DDC_SDA_WRITE_MASK (1 << 4) + +/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. + * From KGI originally. */ +struct riva_regs { + u8 attr[NUM_ATC_REGS]; + u8 crtc[NUM_CRT_REGS]; + u8 gra[NUM_GRC_REGS]; + u8 seq[NUM_SEQ_REGS]; + u8 misc_output; + RIVA_HW_STATE ext; +}; + +struct riva_par; + +struct riva_i2c_chan { + struct riva_par *par; + unsigned long ddc_base; + struct i2c_adapter adapter; + struct i2c_algo_bit_data algo; +}; + +struct riva_par { + RIVA_HW_INST riva; /* interface to riva_hw.c */ + u32 pseudo_palette[16]; /* default palette */ + u32 palette[16]; /* for Riva128 */ + u8 __iomem *ctrl_base; /* virtual control register base addr */ + unsigned dclk_max; /* max DCLK */ + + struct riva_regs initial_state; /* initial startup video mode */ + struct riva_regs current_state; +#ifdef CONFIG_X86 + struct vgastate state; +#endif + struct mutex open_lock; + unsigned int ref_count; + unsigned char *EDID; + unsigned int Chipset; + int forceCRTC; + Bool SecondCRTC; + int FlatPanel; + struct pci_dev *pdev; + int cursor_reset; +#ifdef CONFIG_MTRR + struct { int vram; int vram_valid; } mtrr; +#endif + struct riva_i2c_chan chan[3]; +}; + +void riva_common_setup(struct riva_par *); +unsigned long riva_get_memlen(struct riva_par *); +unsigned long riva_get_maxdclk(struct riva_par *); +void riva_delete_i2c_busses(struct riva_par *par); +void riva_create_i2c_busses(struct riva_par *par); +int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid); + +#endif /* __RIVAFB_H */ |