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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2018-04-22 13:53:30 +0300
committerLinus Walleij <linus.walleij@linaro.org>2018-05-02 15:36:08 +0300
commitbf6f146f3221596d7e44dd3547b9d22782e31504 (patch)
tree54f94dc6eca7455a7aa21d06228528d2dcc71763 /drivers/vfio
parentb0d46cb598bed0b03921090ba5fb84ceb4c6f707 (diff)
downloadlinux-bf6f146f3221596d7e44dd3547b9d22782e31504.tar.xz
pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and TXD2/TXD3 signals
These are only available on the Meson8m2 SoC (which uses the same DesignWare Ethernet MAC as Meson8b). The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII PHYs or the RGMII TX clock (as far as we know the frequency is controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP block). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/vfio')
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