diff options
| author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2010-07-19 12:40:50 +0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-08-11 01:35:43 +0400 |
| commit | e50bf385bfadeaacfb8af07b9b78dcfdef339981 (patch) | |
| tree | 22814cd0fb63f6bf0e10966685b50af14d3db13e /drivers/usb/gadget/s3c-hsotg.c | |
| parent | a33e7136e9652374f7d54ded3cff8062d8e1e84f (diff) | |
| download | linux-e50bf385bfadeaacfb8af07b9b78dcfdef339981.tar.xz | |
USB: s3c-hsotg: Add support for external USB clock
The PLL that drives the USB clock supports 3 input clocks: 12, 24 and 48Mhz.
This patch adds support to the USB driver for setting the correct register bit
according to the given clock.
This depends on the following patch:
[PATCH] ARM: S3C64XX: Add USB external clock definition
Signed-off-by: Maurus Cuelenaere <mcuelenaere@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/gadget/s3c-hsotg.c')
| -rw-r--r-- | drivers/usb/gadget/s3c-hsotg.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c index 825b6ca62941..a4e0b0fa0191 100644 --- a/drivers/usb/gadget/s3c-hsotg.c +++ b/drivers/usb/gadget/s3c-hsotg.c @@ -25,6 +25,7 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/slab.h> +#include <linux/clk.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> @@ -2798,6 +2799,7 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg, */ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) { + struct clk *xusbxti; u32 osc; writel(0, S3C_PHYPWR); @@ -2805,6 +2807,23 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0; + xusbxti = clk_get(hsotg->dev, "xusbxti"); + if (xusbxti && !IS_ERR(xusbxti)) { + switch (clk_get_rate(xusbxti)) { + case 12*MHZ: + osc |= S3C_PHYCLK_CLKSEL_12M; + break; + case 24*MHZ: + osc |= S3C_PHYCLK_CLKSEL_24M; + break; + default: + case 48*MHZ: + /* default reference clock */ + break; + } + clk_put(xusbxti); + } + writel(osc | 0x10, S3C_PHYCLK); /* issue a full set of resets to the otg and core */ |