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author | Grigor Tovmasyan <Grigor.Tovmasyan@synopsys.com> | 2018-08-29 19:59:34 +0300 |
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committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2018-10-02 10:49:26 +0300 |
commit | ca531bc2bfa655a1a0acaac4f7a6ea4b2111cc43 (patch) | |
tree | 0ab12ee7395a4d56128687d45a9b7bf4d23051d1 /drivers/usb/dwc2/core.h | |
parent | c464da0bff6ab6fd39b4603d017de940832bc388 (diff) | |
download | linux-ca531bc2bfa655a1a0acaac4f7a6ea4b2111cc43.tar.xz |
usb: dwc2: Add core parameter for service interval support
Added core parameter for service interval based scheduling.
Acked-by: Minas Harutyunyan <hminas@synopsys.com>
Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/dwc2/core.h')
-rw-r--r-- | drivers/usb/dwc2/core.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index cc9c93affa14..2678dc9d559b 100644 --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -416,6 +416,9 @@ enum dwc2_ep0_state { * back to DWC2_SPEED_PARAM_HIGH while device is gone. * 0 - No (default) * 1 - Yes + * @service_interval: Enable service interval based scheduling. + * 0 - No + * 1 - Yes * * The following parameters may be specified when starting the module. These * parameters define how the DWC_otg controller should be configured. A @@ -461,6 +464,7 @@ struct dwc2_core_params { bool lpm_clock_gating; bool besl; bool hird_threshold_en; + bool service_interval; u8 hird_threshold; bool activate_stm_fs_transceiver; bool ipg_isoc_en; @@ -605,6 +609,10 @@ struct dwc2_core_params { * FIFO sizing is enabled 16 to 32768 * Actual maximum value is autodetected and also * the default. + * @service_interval_mode: For enabling service interval based scheduling in the + * controller. + * 0 - Disable + * 1 - Enable */ struct dwc2_hw_params { unsigned op_mode:3; @@ -635,6 +643,7 @@ struct dwc2_hw_params { unsigned utmi_phy_data_width:2; unsigned lpm_mode:1; unsigned ipg_isoc_en:1; + unsigned service_interval_mode:1; u32 snpsid; u32 dev_ep_dirs; u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; |