diff options
| author | Sudhakar Mamillapalli <sudhakar@fb.com> | 2012-04-11 01:10:58 +0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-04-19 03:26:17 +0400 |
| commit | 0ad372b962d109323d18ac2aa118b2ad100eb8dd (patch) | |
| tree | 82a9c1308720f9a96ff1432c063125a0695160d4 /drivers/tty/serial/8250/8250.c | |
| parent | 665ab0f3c8b8f86bb77b25285ac93870c7054d63 (diff) | |
| download | linux-0ad372b962d109323d18ac2aa118b2ad100eb8dd.tar.xz | |
serial/8250_pci: Clear FIFOs for Intel ME Serial Over Lan device on BI
When using Serial Over Lan (SOL) over the virtual serial port in a Intel
management engine (ME) device, on device reset the serial FIFOs need to
be cleared to keep the FIFO indexes in-sync between the host and the
engine.
On a reset the serial device assertes BI, so using that as a cue FIFOs
are cleared. So for this purpose a new handle_break callback has been
added. One other problem is that the serial registers might temporarily
go to 0 on reset of this device. So instead of using the IER register
read, if 0 returned use the ier value in uart_8250_port. This is hidden
under a custom serial_in.
Cc: Nhan H Mai <nhan.h.mai@intel.com>
Signed-off-by: Sudhakar Mamillapalli <sudhakar@fb.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/8250/8250.c')
| -rw-r--r-- | drivers/tty/serial/8250/8250.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c index cbd94c3b5702..182efcc90e2e 100644 --- a/drivers/tty/serial/8250/8250.c +++ b/drivers/tty/serial/8250/8250.c @@ -568,6 +568,16 @@ static void serial8250_clear_fifos(struct uart_8250_port *p) } } +void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) +{ + unsigned char fcr; + + serial8250_clear_fifos(p); + fcr = uart_config[p->port.type].fcr; + serial_out(p, UART_FCR, fcr); +} +EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); + /* * IER sleep support. UARTs which have EFRs need the "extended * capability" bit enabled. Note that on XR16C850s, we need to |