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| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2022-08-15 19:59:43 +0300 |
|---|---|---|
| committer | Mika Westerberg <mika.westerberg@linux.intel.com> | 2022-09-05 09:02:16 +0300 |
| commit | b12d2955e732866dd8c73154992332a01e7224ed (patch) | |
| tree | 54b7fe61466fe8784295ff969f263b500f7df5f5 /drivers/thunderbolt/tb_regs.h | |
| parent | 3846d011403b57190b6b3e917cc8b3ab810fa293 (diff) | |
| download | linux-b12d2955e732866dd8c73154992332a01e7224ed.tar.xz | |
thunderbolt: Add helper to check if CL states are enabled on port
We will need this when enabling lane margining support.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt/tb_regs.h')
| -rw-r--r-- | drivers/thunderbolt/tb_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h index a45f295533cd..0fe1daa21423 100644 --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h @@ -334,6 +334,7 @@ struct tb_regs_port_header { #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3 #define LANE_ADP_CS_1_CL0S_ENABLE BIT(10) #define LANE_ADP_CS_1_CL1_ENABLE BIT(11) +#define LANE_ADP_CS_1_CL2_ENABLE BIT(12) #define LANE_ADP_CS_1_LD BIT(14) #define LANE_ADP_CS_1_LB BIT(15) #define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16) |