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| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2020-03-04 18:09:14 +0300 |
|---|---|---|
| committer | Mika Westerberg <mika.westerberg@linux.intel.com> | 2020-06-22 19:58:20 +0300 |
| commit | bbcf40b3928347d4bff0017246f7fc840405e92f (patch) | |
| tree | 24d5cba0be6d32a5d60f969719055a3be31a0061 /drivers/thunderbolt/tb_regs.h | |
| parent | e876f34adc185ee8f66c13bad13b2b9b080b3ba9 (diff) | |
| download | linux-bbcf40b3928347d4bff0017246f7fc840405e92f.tar.xz | |
thunderbolt: Do not tunnel USB3 if link is not USB4
USB3 tunneling is possible only over USB4 link so don't create USB3
tunnels if that's not the case.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt/tb_regs.h')
| -rw-r--r-- | drivers/thunderbolt/tb_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h index c29c5075525a..77d4b8598835 100644 --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h @@ -290,6 +290,7 @@ struct tb_regs_port_header { /* USB4 port registers */ #define PORT_CS_18 0x12 #define PORT_CS_18_BE BIT(8) +#define PORT_CS_18_TCM BIT(9) #define PORT_CS_19 0x13 #define PORT_CS_19_PC BIT(3) |