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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2018-08-08 13:51:00 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-08-08 19:08:07 +0300 |
| commit | a4a717010f4e8cacaa3f0cae8a22f25c39ae1d41 (patch) | |
| tree | 7d603927f9da1b5e18c460cc7c69404a1107e078 /drivers/thermal/zx2967_thermal.c | |
| parent | c1e63f6df3d3e9e4d0da67f6c8aabdfbe592371f (diff) | |
| download | linux-a4a717010f4e8cacaa3f0cae8a22f25c39ae1d41.tar.xz | |
drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw
An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably
Valleyview) in that for the period following the GPU restart after a
reset, there are no GT interrupts received. From Ville's notes, bit 0 in
the HWSTAM corresponds to the render interrupt, and if we unmask it we
do see immediate resumption of GT interrupt delivery (via the master irq
handler) after the reset.
v2: Limit the w/a to the render interrupt from rcs
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500
Fixes: c5498089463b ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode")
References: d420a50c21ef ("drm/i915: Clean up the HWSTAM mess")
Testcase: igt/gem_eio/reset-stress
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180808105101.913-2-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/thermal/zx2967_thermal.c')
0 files changed, 0 insertions, 0 deletions