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| author | Thierry Reding <treding@nvidia.com> | 2016-09-01 14:46:17 +0300 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2016-09-26 22:31:23 +0300 |
| commit | 4ae12588e028f66a505b2287e8237a1815ee31a3 (patch) | |
| tree | 983cdc2ecc4425ec66e3ad5ea3af464ab8c18235 /drivers/thermal/thermal_core.h | |
| parent | b2ca77c98390304722c2baf289b181d6f0fa3c49 (diff) | |
| download | linux-4ae12588e028f66a505b2287e8237a1815ee31a3.tar.xz | |
mmc: tegra: Mark 64-bit DMA broken on Tegra124
According to the TRM, the SD/MMC controller on Tegra124 supports 34-bit
addressing, but testing shows that this doesn't work. On a device which
has more than 2 GiB of RAM and LPAE enabled, buffer allocations can use
addresses above the 32-bit boundary.
One way to work around this would be to enable IOMMU physical to virtual
address translations for the SD/MMC controllers, but that's not easy to
implement without breaking existing use-cases. It's also not obvious why
34-bit addressing doesn't work as advertised. In order to fix this for
existing users, add the SDHCI_QUIRK2_BROKEN_64_BIT_DMA quirk for now.
Reported-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/thermal/thermal_core.h')
0 files changed, 0 insertions, 0 deletions