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| author | James Bottomley <JBottomley@Parallels.com> | 2011-07-23 21:09:03 +0400 |
|---|---|---|
| committer | James Bottomley <JBottomley@Parallels.com> | 2011-07-23 21:09:03 +0400 |
| commit | 87045b033a62777337ae4aa62834876da09b5fb5 (patch) | |
| tree | 26aefd28e436668ff906e42b1e0d75c056e33e01 /drivers/ssb/driver_pcicore.c | |
| parent | 0d83ab65ff1b54ce8b6cd172285cf71a38c4cceb (diff) | |
| parent | bfe159a51203c15d23cb3158fffdc25ec4b4dda1 (diff) | |
| download | linux-87045b033a62777337ae4aa62834876da09b5fb5.tar.xz | |
Merge branch 'scsi-fixes'
Diffstat (limited to 'drivers/ssb/driver_pcicore.c')
| -rw-r--r-- | drivers/ssb/driver_pcicore.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c index 2a20dabec76d..d6620ad309ce 100644 --- a/drivers/ssb/driver_pcicore.c +++ b/drivers/ssb/driver_pcicore.c @@ -516,8 +516,17 @@ static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc) static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) { + ssb_pcicore_fix_sprom_core_index(pc); + /* Disable PCI interrupts. */ ssb_write32(pc->dev, SSB_INTVEC, 0); + + /* Additional PCIe always once-executed workarounds */ + if (pc->dev->id.coreid == SSB_DEV_PCIE) { + ssb_pcicore_serdes_workaround(pc); + /* TODO: ASPM */ + /* TODO: Clock Request Update */ + } } void ssb_pcicore_init(struct ssb_pcicore *pc) @@ -529,8 +538,6 @@ void ssb_pcicore_init(struct ssb_pcicore *pc) if (!ssb_device_is_enabled(dev)) ssb_device_enable(dev, 0); - ssb_pcicore_fix_sprom_core_index(pc); - #ifdef CONFIG_SSB_PCICORE_HOSTMODE pc->hostmode = pcicore_is_in_hostmode(pc); if (pc->hostmode) @@ -538,13 +545,6 @@ void ssb_pcicore_init(struct ssb_pcicore *pc) #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ if (!pc->hostmode) ssb_pcicore_init_clientmode(pc); - - /* Additional PCIe always once-executed workarounds */ - if (dev->id.coreid == SSB_DEV_PCIE) { - ssb_pcicore_serdes_workaround(pc); - /* TODO: ASPM */ - /* TODO: Clock Request Update */ - } } static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) |