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| author | Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> | 2015-01-23 19:08:33 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-01-26 22:23:35 +0300 |
| commit | bca690db90b832a58756b30d5ff41e65881216f9 (patch) | |
| tree | 6033fd52c122c9269c6406d0f2be56423bb80b95 /drivers/spi | |
| parent | 97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff) | |
| download | linux-bca690db90b832a58756b30d5ff41e65881216f9.tar.xz | |
spi/xilinx: Support for spi mode LSB_FIRST
Hardware supports LSB_FIRST mode. Support it also in the driver.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-xilinx.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c index 79bd84f43430..d4edeeeabbc3 100644 --- a/drivers/spi/spi-xilinx.c +++ b/drivers/spi/spi-xilinx.c @@ -34,7 +34,8 @@ #define XSPI_CR_MASTER_MODE 0x04 #define XSPI_CR_CPOL 0x08 #define XSPI_CR_CPHA 0x10 -#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) +#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \ + XSPI_CR_LSB_FIRST) #define XSPI_CR_TXFIFO_RESET 0x20 #define XSPI_CR_RXFIFO_RESET 0x40 #define XSPI_CR_MANUAL_SSELECT 0x80 @@ -194,6 +195,8 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) cr |= XSPI_CR_CPHA; if (spi->mode & SPI_CPOL) cr |= XSPI_CR_CPOL; + if (spi->mode & SPI_LSB_FIRST) + cr |= XSPI_CR_LSB_FIRST; xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); /* We do not check spi->max_speed_hz here as the SPI clock @@ -353,7 +356,7 @@ static int xilinx_spi_probe(struct platform_device *pdev) return -ENODEV; /* the spi->mode bits understood by this driver: */ - master->mode_bits = SPI_CPOL | SPI_CPHA; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; xspi = spi_master_get_devdata(master); xspi->bitbang.master = master; |