diff options
| author | Chris Blair <chris.blair@stericsson.com> | 2011-06-04 10:57:47 +0400 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2011-12-01 20:16:07 +0400 |
| commit | 172289df4004cccf798316b19cc3e6284dbe901f (patch) | |
| tree | ee82043bd2a819a81416730ba7ac2c882bbb311c /drivers/spi | |
| parent | caca6a03d365883564885f2c1da3e88dcf65d139 (diff) | |
| download | linux-172289df4004cccf798316b19cc3e6284dbe901f.tar.xz | |
spi/pl022: only enable RX interrupts when TX is complete
For interrupt mode transfers, start with only TX interrupts enabled
to reduce the overall number of interrupts received. Once TX is
complete, enable RX interrupts to complete the transfer.
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Chris Blair <chris.blair@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-pl022.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index 5559b2299198..5b7209f9f100 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -1244,9 +1244,9 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) if ((pl022->tx == pl022->tx_end) && (flag == 0)) { flag = 1; - /* Disable Transmit interrupt */ - writew(readw(SSP_IMSC(pl022->virtbase)) & - (~SSP_IMSC_MASK_TXIM), + /* Disable Transmit interrupt, enable receive interrupt */ + writew((readw(SSP_IMSC(pl022->virtbase)) & + ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); } @@ -1379,12 +1379,17 @@ static void pump_transfers(unsigned long data) } err_config_dma: - writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); + /* enable all interrupts except RX */ + writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); } static void do_interrupt_dma_transfer(struct pl022 *pl022) { - u32 irqflags = ENABLE_ALL_INTERRUPTS; + /* + * Default is to enable all interrupts except RX - + * this will be enabled once TX is complete + */ + u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; /* Enable target chip */ pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |