diff options
| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2013-07-03 14:25:06 +0400 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2013-07-15 14:42:23 +0400 |
| commit | 1de7061253a2742c743f3883f0e73480c9bceee0 (patch) | |
| tree | b9bd9435bb1c76608d1bb5077f011f2057337d4b /drivers/spi/spi-pxa2xx.c | |
| parent | ad81f0545ef01ea651886dddac4bef6cec930092 (diff) | |
| download | linux-1de7061253a2742c743f3883f0e73480c9bceee0.tar.xz | |
spi/pxa2xx: enable DMA on newer Intel LPSS silicon
There is an additional bit in the Intel LPSS SPI private registers that
needs to be set in order to be able to use DMA with the SPI controller.
Enable this as well.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'drivers/spi/spi-pxa2xx.c')
| -rw-r--r-- | drivers/spi/spi-pxa2xx.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index f440dcee852b..e0fd6f63c93e 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -69,6 +69,8 @@ MODULE_ALIAS("platform:pxa2xx-spi"); #define LPSS_TX_HITHRESH_DFLT 224 /* Offset from drv_data->lpss_base */ +#define GENERAL_REG 0x08 +#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) #define SSP_REG 0x0c #define SPI_CS_CONTROL 0x18 #define SPI_CS_CONTROL_SW_MODE BIT(0) @@ -142,8 +144,13 @@ detection_done: __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); /* Enable multiblock DMA transfers */ - if (drv_data->master_info->enable_dma) + if (drv_data->master_info->enable_dma) { __lpss_ssp_write_priv(drv_data, SSP_REG, 1); + + value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); + value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; + __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); + } } static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) |