diff options
| author | Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> | 2020-11-24 07:18:38 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-01-13 14:37:03 +0300 |
| commit | b436fb7d29bfa48ff5e00cbf413609c7a6d4d81e (patch) | |
| tree | 8652413cc4a84342ee2fa81ffeedeb65008cd3e0 /drivers/spi/spi-cadence-quadspi.c | |
| parent | ad2775dc3fc5d30dd51984ccbaa736cc7ea9caca (diff) | |
| download | linux-b436fb7d29bfa48ff5e00cbf413609c7a6d4d81e.tar.xz | |
spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20201124041840.31066-4-vadivel.muruganx.ramuthevar@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-cadence-quadspi.c')
| -rw-r--r-- | drivers/spi/spi-cadence-quadspi.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 8c5e83898ae2..b7ecbc8c1caa 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -76,6 +76,7 @@ struct cqspi_st { bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; + u32 num_chipselect; bool rclk_en; u32 trigger_address; u32 wr_delay; @@ -1353,6 +1354,9 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) return -ENXIO; } + if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) + cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; + cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); return 0; @@ -1589,6 +1593,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->current_cs = -1; cqspi->sclk = 0; + master->num_chipselect = cqspi->num_chipselect; + ret = cqspi_setup_flash(cqspi); if (ret) { dev_err(dev, "failed to setup flash parameters %d\n", ret); |