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authorPetlozu Pravareshwar <petlozup@nvidia.com>2022-10-02 17:44:09 +0300
committerThierry Reding <treding@nvidia.com>2022-11-10 04:55:23 +0300
commit0474cc8489bda9a8cd6a10252e7e6af29c849438 (patch)
treeed9a1cdbec9734ce4f6998d0c85a7fe1d7cd30d7 /drivers/soc/tegra
parent1ddb8f6d44ff482c9953a06f800453bc372cfead (diff)
downloadlinux-0474cc8489bda9a8cd6a10252e7e6af29c849438.tar.xz
soc/tegra: pmc: Process wake events during resume
During system resume, translate tier2 SC7 wake sources back into IRQs and do generic_handle_irq() to invoke the interrupt handlers for edge triggered wake events such as SW-wake. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/soc/tegra')
-rw-r--r--drivers/soc/tegra/pmc.c41
1 files changed, 41 insertions, 0 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 767f33303617..cf4cfbf9f7c5 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -23,6 +23,7 @@
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
+#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/irqdomain.h>
@@ -3147,6 +3148,45 @@ static void wke_clear_wake_status(struct tegra_pmc *pmc)
}
}
+/* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */
+static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index,
+ unsigned long status)
+{
+ unsigned int wake;
+
+ dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status);
+
+ for_each_set_bit(wake, &status, 32) {
+ irq_hw_number_t hwirq = wake + 32 * index;
+ struct irq_desc *desc;
+ unsigned int irq;
+
+ irq = irq_find_mapping(pmc->domain, hwirq);
+
+ desc = irq_to_desc(irq);
+ if (!desc || !desc->action || !desc->action->name) {
+ dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq);
+ continue;
+ }
+
+ dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name);
+ generic_handle_irq(irq);
+ }
+}
+
+static void tegra186_pmc_wake_syscore_resume(void)
+{
+ u32 status, mask;
+ unsigned int i;
+
+ for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
+ mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
+ status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
+
+ tegra186_pmc_process_wake_events(pmc, i, status);
+ }
+}
+
static int tegra186_pmc_wake_syscore_suspend(void)
{
wke_read_sw_wake_status(pmc);
@@ -3812,6 +3852,7 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = {
static void tegra186_pmc_init(struct tegra_pmc *pmc)
{
pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend;
+ pmc->syscore.resume = tegra186_pmc_wake_syscore_resume;
register_syscore_ops(&pmc->syscore);
}