diff options
| author | John Garry <john.garry@huawei.com> | 2016-10-04 14:11:11 +0300 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2016-11-09 01:29:46 +0300 |
| commit | 3bc45af81d0dff722c5a2d5d009f2d2d91b52b56 (patch) | |
| tree | 3bf9b1a03b0af9c1b510ab7c2320eaddca0dd4bd /drivers/scsi/hisi_sas/hisi_sas.h | |
| parent | 039ae102a8d43bbaa00e678b37f58310f4674650 (diff) | |
| download | linux-3bc45af81d0dff722c5a2d5d009f2d2d91b52b56.tar.xz | |
scsi: hisi_sas: Add v2 hw support for different refclk
The hip06 D03 and hip07 D05 boards have different reference clock
frequencies for the SAS controller.
Register PHY_CTRL needs to be programmed differently according to this
frequency, so add support for this.
The default register setting in PHY_CTRL is for 50MHz, so only update
this register when the refclk frequency is 66MHz.
For ACPI we expect the _RST handler to set the correct value for
PHY_CTRL (we're forced to take different approach for DT and ACPI as
ACPI does not support fixed-clock device).
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/hisi_sas/hisi_sas.h')
| -rw-r--r-- | drivers/scsi/hisi_sas/hisi_sas.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 72c98522bd26..64046c5853a5 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -13,6 +13,7 @@ #define _HISI_SAS_H_ #include <linux/acpi.h> +#include <linux/clk.h> #include <linux/dmapool.h> #include <linux/mfd/syscon.h> #include <linux/module.h> @@ -183,6 +184,7 @@ struct hisi_hba { u32 ctrl_reset_reg; u32 ctrl_reset_sts_reg; u32 ctrl_clock_ena_reg; + u32 refclk_frequency_mhz; u8 sas_addr[SAS_ADDR_SIZE]; int n_phy; |