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author | Jiri Kosina <jkosina@suse.cz> | 2010-04-23 04:08:44 +0400 |
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committer | Jiri Kosina <jkosina@suse.cz> | 2010-04-23 04:08:44 +0400 |
commit | 6c9468e9eb1252eaefd94ce7f06e1be9b0b641b1 (patch) | |
tree | 797676a336b050bfa1ef879377c07e541b9075d6 /drivers/scsi/bfa/include/bfi/bfi_ctreg.h | |
parent | 4cb3ca7cd7e2cae8d1daf5345ec99a1e8502cf3f (diff) | |
parent | c81eddb0e3728661d1585fbc564449c94165cc36 (diff) | |
download | linux-6c9468e9eb1252eaefd94ce7f06e1be9b0b641b1.tar.xz |
Merge branch 'master' into for-next
Diffstat (limited to 'drivers/scsi/bfa/include/bfi/bfi_ctreg.h')
-rw-r--r-- | drivers/scsi/bfa/include/bfi/bfi_ctreg.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/scsi/bfa/include/bfi/bfi_ctreg.h b/drivers/scsi/bfa/include/bfi/bfi_ctreg.h index d3caa58c0a0a..57a8497105af 100644 --- a/drivers/scsi/bfa/include/bfi/bfi_ctreg.h +++ b/drivers/scsi/bfa/include/bfi/bfi_ctreg.h @@ -430,6 +430,31 @@ enum { #define __PSS_LMEM_INIT_EN 0x00000100 #define __PSS_LPU1_RESET 0x00000002 #define __PSS_LPU0_RESET 0x00000001 +#define PSS_ERR_STATUS_REG 0x00018810 +#define __PSS_LPU1_TCM_READ_ERR 0x00200000 +#define __PSS_LPU0_TCM_READ_ERR 0x00100000 +#define __PSS_LMEM5_CORR_ERR 0x00080000 +#define __PSS_LMEM4_CORR_ERR 0x00040000 +#define __PSS_LMEM3_CORR_ERR 0x00020000 +#define __PSS_LMEM2_CORR_ERR 0x00010000 +#define __PSS_LMEM1_CORR_ERR 0x00008000 +#define __PSS_LMEM0_CORR_ERR 0x00004000 +#define __PSS_LMEM5_UNCORR_ERR 0x00002000 +#define __PSS_LMEM4_UNCORR_ERR 0x00001000 +#define __PSS_LMEM3_UNCORR_ERR 0x00000800 +#define __PSS_LMEM2_UNCORR_ERR 0x00000400 +#define __PSS_LMEM1_UNCORR_ERR 0x00000200 +#define __PSS_LMEM0_UNCORR_ERR 0x00000100 +#define __PSS_BAL_PERR 0x00000080 +#define __PSS_DIP_IF_ERR 0x00000040 +#define __PSS_IOH_IF_ERR 0x00000020 +#define __PSS_TDS_IF_ERR 0x00000010 +#define __PSS_RDS_IF_ERR 0x00000008 +#define __PSS_SGM_IF_ERR 0x00000004 +#define __PSS_LPU1_RAM_ERR 0x00000002 +#define __PSS_LPU0_RAM_ERR 0x00000001 +#define ERR_SET_REG 0x00018818 +#define __PSS_ERR_STATUS_SET 0x003fffff #define HQM_QSET0_RXQ_DRBL_P0 0x00038000 #define __RXQ0_ADD_VECTORS_P 0x80000000 #define __RXQ0_STOP_P 0x40000000 @@ -589,6 +614,7 @@ enum { #define __HFN_INT_MBOX_LPU1 0x00200000U #define __HFN_INT_MBOX1_LPU0 0x00400000U #define __HFN_INT_MBOX1_LPU1 0x00800000U +#define __HFN_INT_LL_HALT 0x01000000U #define __HFN_INT_CPE_MASK 0x000000ffU #define __HFN_INT_RME_MASK 0x0000ff00U |