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| author | Paolo Bonzini <pbonzini@redhat.com> | 2021-04-22 09:39:48 +0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-04-22 20:19:01 +0300 |
| commit | fd49e8ee70b306a003323a17bbcc0633f322c135 (patch) | |
| tree | be0e5f131ee5afdbaa7a6b5fc76bb36baad8c067 /drivers/platform/x86/Kconfig | |
| parent | 238eca821cee90e91139da84ef4f38c74d7cf0d9 (diff) | |
| parent | 7aef27f0b2a8a58c28578d3e0caf3f27e1a1c39c (diff) | |
| download | linux-fd49e8ee70b306a003323a17bbcc0633f322c135.tar.xz | |
Merge branch 'kvm-sev-cgroup' into HEAD
Diffstat (limited to 'drivers/platform/x86/Kconfig')
| -rw-r--r-- | drivers/platform/x86/Kconfig | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index ad4e630e73e2..461ec61530eb 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -1173,15 +1173,20 @@ config INTEL_PMC_CORE depends on PCI help The Intel Platform Controller Hub for Intel Core SoCs provides access - to Power Management Controller registers via a PCI interface. This + to Power Management Controller registers via various interfaces. This driver can utilize debugging capabilities and supported features as - exposed by the Power Management Controller. + exposed by the Power Management Controller. It also may perform some + tasks in the PMC in order to enable transition into the SLPS0 state. + It should be selected on all Intel platforms supported by the driver. Supported features: - SLP_S0_RESIDENCY counter - PCH IP Power Gating status - - LTR Ignore + - LTR Ignore / LTR Show - MPHY/PLL gating status (Sunrisepoint PCH only) + - SLPS0 Debug registers (Cannonlake/Icelake PCH) + - Low Power Mode registers (Tigerlake and beyond) + - PMC quirks as needed to enable SLPS0/S0ix config INTEL_PMT_CLASS tristate |