diff options
| author | Agrawal, Nitesh-kumar <Nitesh-kumar.Agrawal@amd.com> | 2016-08-31 11:50:49 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2016-09-07 22:48:16 +0300 |
| commit | 499c7196dd182ba513ccb9620ee22aed3f9096fd (patch) | |
| tree | 37865dea68ee00cb2a63d2c41d329fab19ba3db0 /drivers/pinctrl | |
| parent | ac91ab51e4f882db65449ff821a5664bad4b164c (diff) | |
| download | linux-499c7196dd182ba513ccb9620ee22aed3f9096fd.tar.xz | |
pinctrl/amd: Configure GPIO register using BIOS settings
In the function amd_gpio_irq_set_type, use the settings provided by
the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure
the GPIO registers. Ignore the settings from client.
Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com>
Signed-off-by:Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/pinctrl-amd.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 634b4d30eefb..962746e6ab04 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -403,12 +403,27 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) int ret = 0; u32 pin_reg; unsigned long flags; + u32 level_trig; + u32 active_level; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + /* + * When level_trig is set EDGE and active_level is set HIGH in BIOS + * default settings, ignore incoming settings from client and use + * BIOS settings to configure GPIO register. + */ + level_trig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF); + active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); + + if((!level_trig) && + ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) { + type = IRQ_TYPE_EDGE_FALLING; + } + switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: pin_reg &= ~BIT(LEVEL_TRIG_OFF); |