diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-07-31 09:21:07 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-08-14 16:01:00 +0300 |
| commit | e3829d15460feb884805012c72ec4a17402822eb (patch) | |
| tree | d5d178991f09be26699a4f5bdb875b8444f90837 /drivers/pinctrl/uniphier | |
| parent | 9fc939c68325752580ffcf966e9da49a7ab94a90 (diff) | |
| download | linux-e3829d15460feb884805012c72ec4a17402822eb.tar.xz | |
pinctrl: uniphier: fix pin_config_get() for input-enable
For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are
located across multiple registers. So, the register offset must be
taken into account. Otherwise, wrong input-enable status is displayed.
While we here, rename the macro because it is a base address.
Fixes: aa543888ca8c ("pinctrl: uniphier: support per-pin input enable for new SoCs")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/uniphier')
| -rw-r--r-- | drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index c649e835bd54..f2f0f9dcfec3 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -32,7 +32,7 @@ #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00 -#define UNIPHIER_PINCTRL_IECTRL 0x1d00 +#define UNIPHIER_PINCTRL_IECTRL_BASE 0x1d00 struct uniphier_pinctrl_priv { struct pinctrl_desc pctldesc; @@ -252,18 +252,21 @@ static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev, { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data); - unsigned int val; + unsigned int reg, mask, val; int ret; if (iectrl == UNIPHIER_PIN_IECTRL_NONE) /* This pin is always input-enabled. */ return 0; - ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val); + reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; + mask = BIT(iectrl % 32); + + ret = regmap_read(priv->regmap, reg, &val); if (ret) return ret; - return val & BIT(iectrl) ? 0 : -EINVAL; + return val & mask ? 0 : -EINVAL; } static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev, @@ -456,7 +459,7 @@ static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev, if (iectrl == UNIPHIER_PIN_IECTRL_NONE) return enable ? 0 : -EINVAL; - reg = UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4; + reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; mask = BIT(iectrl % 32); return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0); |