diff options
| author | Thierry Reding <treding@nvidia.com> | 2017-11-07 21:15:47 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-11-08 16:06:21 +0300 |
| commit | f0fbe7bce733561b76a5b55c5f4625888acd3792 (patch) | |
| tree | 396ecdc63cab3227779a28cf43a5a3e2c7cfe3b1 /drivers/pinctrl/sirf | |
| parent | da80ff81a8f54611b834d73149f8ac0d59151c87 (diff) | |
| download | linux-f0fbe7bce733561b76a5b55c5f4625888acd3792.tar.xz | |
gpio: Move irqdomain into struct gpio_irq_chip
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sirf')
| -rw-r--r-- | drivers/pinctrl/sirf/pinctrl-atlas7.c | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/sirf/pinctrl-sirf.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 4db9323251e3..f5cef6e5fa3e 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -5820,7 +5820,7 @@ static void atlas7_gpio_handle_irq(struct irq_desc *desc) __func__, gc->label, bank->gpio_offset + pin_in_bank); generic_handle_irq( - irq_find_mapping(gc->irqdomain, + irq_find_mapping(gc->irq.domain, bank->gpio_offset + pin_in_bank)); } diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index d3ef05973901..8b14a1f1e671 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -587,7 +587,7 @@ static void sirfsoc_gpio_handle_irq(struct irq_desc *desc) if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { pr_debug("%s: gpio id %d idx %d happens\n", __func__, bank->id, idx); - generic_handle_irq(irq_find_mapping(gc->irqdomain, idx + + generic_handle_irq(irq_find_mapping(gc->irq.domain, idx + bank->id * SIRFSOC_GPIO_BANK_SIZE)); } |