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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-12-18 22:48:09 +0300 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-12-31 11:57:40 +0300 |
commit | 55b1cb1f03ad5eea39897d0c74035e02deddcff2 (patch) | |
tree | 8aac4a0dc18e2ffa9f355e0e0e1f7f4b57df0c73 /drivers/pinctrl/sh-pfc/Kconfig | |
parent | 2a069a92811fb35b57aaa1bfbe406afcc723f490 (diff) | |
download | linux-55b1cb1f03ad5eea39897d0c74035e02deddcff2.tar.xz |
pinctrl: sh-pfc: sh7264: Fix CAN function GPIOs
pinmux_func_gpios[] contains a hole due to the missing function GPIO
definition for the "CTX0&CTX1" signal, which is the logical "AND" of the
two CAN outputs.
Fix this by:
- Renaming CRX0_CRX1_MARK to CTX0_CTX1_MARK, as PJ2MD[2:0]=010
configures the combined "CTX0&CTX1" output signal,
- Renaming CRX0X1_MARK to CRX0_CRX1_MARK, as PJ3MD[1:0]=10 configures
the shared "CRX0/CRX1" input signal, which is fed to both CAN
inputs,
- Adding the missing function GPIO definition for "CTX0&CTX1" to
pinmux_func_gpios[],
- Moving all CAN enums next to each other.
See SH7262 Group, SH7264 Group User's Manual: Hardware, Rev. 4.00:
[1] Figure 1.2 (3) (Pin Assignment for the SH7264 Group (1-Mbyte
Version),
[2] Figure 1.2 (4) Pin Assignment for the SH7264 Group (640-Kbyte
Version,
[3] Table 1.4 List of Pins,
[4] Figure 20.29 Connection Example when Using This Module as 1-Channel
Module (64 Mailboxes x 1 Channel),
[5] Table 32.10 Multiplexed Pins (Port J),
[6] Section 32.2.30 (3) Port J Control Register 0 (PJCR0).
Note that the last 2 disagree about PJ2MD[2:0], which is probably the
root cause of this bug. But considering [4], "CTx0&CTx1" in [5] must
be correct, and "CRx0&CRx1" in [6] must be wrong.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-4-geert+renesas@glider.be
Diffstat (limited to 'drivers/pinctrl/sh-pfc/Kconfig')
0 files changed, 0 insertions, 0 deletions