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| author | Andrew Jeffery <andrew@aj.id.au> | 2016-08-30 10:54:26 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2016-09-07 17:53:37 +0300 |
| commit | 56e57cb6c07f124911dfe9a6b496f541ed166931 (patch) | |
| tree | 0c9fe1e43a003097b6e589e2a809a09b25b50ff8 /drivers/pinctrl/aspeed/Kconfig | |
| parent | 524594d40153befc7b0c4600550a5eb312c6918c (diff) | |
| download | linux-56e57cb6c07f124911dfe9a6b496f541ed166931.tar.xz | |
pinctrl: Add pinctrl-aspeed-g5 driver
A small subset of pins and functions are exposed. The selection of pins
and functions is driven by the development of OpenBMC[1] on the
AST2500 SoC, particularly around booting the IBM Witherspoon platform.
[1] https://github.com/openbmc/docs
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/aspeed/Kconfig')
| -rw-r--r-- | drivers/pinctrl/aspeed/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index 1f3d74549381..998eabef3a65 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -14,3 +14,11 @@ config PINCTRL_ASPEED_G4 help Say Y here to enable pin controller support for Aspeed's 4th generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G5 + bool "Aspeed G5 SoC pin control" + depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 5th + generation SoCs. GPIO is provided by a separate GPIO driver. |