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| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2021-03-02 13:54:12 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-03-30 21:05:17 +0300 |
| commit | 982313c38f2f3793b6435ff50997ae96a2274f5a (patch) | |
| tree | 9edd0e1c251a4706433ef4e969478b9116fe64b8 /drivers/phy | |
| parent | ed9e07f815cd66405895781dd29033c1a7b47b8a (diff) | |
| download | linux-982313c38f2f3793b6435ff50997ae96a2274f5a.tar.xz | |
phy: ralink: phy-mt7621-pci: fix XTAL bitmask
When this was rewriten to get mainlined and start to
use 'linux/bitfield.h' headers, XTAL_MASK was wrong.
It must mask three bits but only two were used. Hence
properly fix it to make things work.
Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210302105412.16221-1-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/ralink/phy-mt7621-pci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c index 9a610b414b1f..84ee2b5c2228 100644 --- a/drivers/phy/ralink/phy-mt7621-pci.c +++ b/drivers/phy/ralink/phy-mt7621-pci.c @@ -62,7 +62,7 @@ #define RG_PE1_FRC_MSTCKDIV BIT(5) -#define XTAL_MASK GENMASK(7, 6) +#define XTAL_MASK GENMASK(8, 6) #define MAX_PHYS 2 |