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authorLinus Walleij <linus.walleij@linaro.org>2014-05-12 13:37:17 +0400
committerGrant Likely <grant.likely@linaro.org>2014-11-27 20:22:02 +0300
commita81a6c654bbe129af529d11b4763367af90d1152 (patch)
tree9378c0a0ad4e010db9ef2c3bfd75ce07fa46f32d /drivers/phy
parente99010edb37f5d5bca6a4d4b78d74cddfc0fc5a4 (diff)
downloadlinux-a81a6c654bbe129af529d11b4763367af90d1152.tar.xz
ARM: dt: fix up PL011 device tree bindings
Make the map match the reality, the current binding text is nonsense: - The clock required for the clocking of the serial port must come first and is not optional (as the driver will otherwise proceed to grab and use the apb_pclk as uartclk), and the apb_pclk that clocks the logic must come second as the code will retrieve the first clock by index, whereas the PrimeCell but will explicitly look for "apb_pclk" so this can be specified later, as it is looked up by name. - The pin control state "default" is the only mandated state, the sleep state is entirely optional. We also add an example to avoid further confusion. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Grant Likely <grant.likely@linaro.org>
Diffstat (limited to 'drivers/phy')
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