diff options
| author | Can Guo <quic_cang@quicinc.com> | 2023-12-02 15:36:15 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-12-21 20:09:44 +0300 |
| commit | 5301b7a04040b0a6191856c765146e0a9ab88ebc (patch) | |
| tree | bacfc2219109a698c8189c04f9c2044a0455ad51 /drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | |
| parent | 21a1d02579ae75fd45555b84d20ba55632a14a19 (diff) | |
| download | linux-5301b7a04040b0a6191856c765146e0a9ab88ebc.tar.xz | |
phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings
The registers, which are being touched in current SM8550 UFS PHY settings,
and the values being programmed are mainly the ones working for HS-G4 mode,
meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings.
However, even consider HS-G4 mode only, some of them are incorrect and some
are missing. Rectify the HS-G4 PHY settings by strictly aligning with the
SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings.
Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/1701520577-31163-10-git-send-email-quic_cang@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h index ae220fd04d10..35d497fd9f9a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h @@ -11,6 +11,7 @@ #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 #define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 |