diff options
author | Yaniv Gardi <ygardi@codeaurora.org> | 2015-01-15 17:32:36 +0300 |
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committer | Christoph Hellwig <hch@lst.de> | 2015-01-20 21:43:25 +0300 |
commit | 39e794bff718188cfb9ace2032cbe4fd86048dc6 (patch) | |
tree | faf817c473422c062dbf04657d957bad1e7d395e /drivers/phy/phy-qcom-ufs-i.h | |
parent | adaafaa393ef1900e23f7708e29d023f721c54b3 (diff) | |
download | linux-39e794bff718188cfb9ace2032cbe4fd86048dc6.tar.xz |
phy: qcom-ufs: add support for 20nm phy
This change adds a support for a 20nm qcom-ufs phy that is required in
platforms that use ufs-qcom controller.
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: Dov Levenglick <dovl@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'drivers/phy/phy-qcom-ufs-i.h')
-rw-r--r-- | drivers/phy/phy-qcom-ufs-i.h | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/drivers/phy/phy-qcom-ufs-i.h b/drivers/phy/phy-qcom-ufs-i.h index dac200f4d639..591a39175e8a 100644 --- a/drivers/phy/phy-qcom-ufs-i.h +++ b/drivers/phy/phy-qcom-ufs-i.h @@ -15,15 +15,56 @@ #ifndef UFS_QCOM_PHY_I_H_ #define UFS_QCOM_PHY_I_H_ +#include <linux/module.h> #include <linux/clk.h> +#include <linux/regulator/consumer.h> #include <linux/slab.h> -#include <linux/phy/phy.h> +#include <linux/phy/phy-qcom-ufs.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/delay.h> +#define readl_poll_timeout(addr, val, cond, sleep_us, timeout_us) \ +({ \ + ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \ + might_sleep_if(timeout_us); \ + for (;;) { \ + (val) = readl(addr); \ + if (cond) \ + break; \ + if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \ + (val) = readl(addr); \ + break; \ + } \ + if (sleep_us) \ + usleep_range(DIV_ROUND_UP(sleep_us, 4), sleep_us); \ + } \ + (cond) ? 0 : -ETIMEDOUT; \ +}) + +#define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \ + { \ + .reg_offset = reg, \ + .cfg_value = val, \ + } + #define UFS_QCOM_PHY_NAME_LEN 30 +enum { + MASK_SERDES_START = 0x1, + MASK_PCS_READY = 0x1, +}; + +enum { + OFFSET_SERDES_START = 0x0, +}; + +struct ufs_qcom_phy_stored_attributes { + u32 att; + u32 value; +}; + + struct ufs_qcom_phy_calibration { u32 reg_offset; u32 cfg_value; |