diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2024-03-12 20:14:25 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-03-12 20:14:25 +0300 |
| commit | 538ca00225663b5481effe94e816ff1aa5d49f66 (patch) | |
| tree | 4a5d16612d3b32e5187de4f172e25a2f511ace09 /drivers/pci | |
| parent | cab098b6f2531f26d447abd07ec7a77e2e442ec0 (diff) | |
| parent | 667a006d73fb7320fc6f414b6fe11a998fcf0c28 (diff) | |
| download | linux-538ca00225663b5481effe94e816ff1aa5d49f66.tar.xz | |
Merge branch 'pci/controller/cadence'
- Clear the ARI Capability Next Function Number of the last function
(Jasko-EXT Wojciech)
* pci/controller/cadence:
PCI: cadence: Clear the ARI Capability Next Function Number of the last function
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/controller/cadence/pcie-cadence-ep.c | 14 | ||||
| -rw-r--r-- | drivers/pci/controller/cadence/pcie-cadence.h | 6 |
2 files changed, 19 insertions, 1 deletions
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 2d0a8d78bffb..81c50dc64da9 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -565,7 +565,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) struct cdns_pcie *pcie = &ep->pcie; struct device *dev = pcie->dev; int max_epfs = sizeof(epc->function_num_map) * 8; - int ret, value, epf; + int ret, epf, last_fn; + u32 reg, value; /* * BIT(0) is hardwired to 1, hence function 0 is always enabled @@ -573,6 +574,17 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) */ cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map); + /* + * Next function field in ARI_CAP_AND_CTR register for last function + * should be 0. + * Clearing Next Function Number field for the last function used. + */ + last_fn = find_last_bit(&epc->function_num_map, BITS_PER_LONG); + reg = CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn); + value = cdns_pcie_readl(pcie, reg); + value &= ~CDNS_PCIE_ARI_CAP_NFN_MASK; + cdns_pcie_writel(pcie, reg, value); + if (ep->quirk_disable_flr) { for (epf = 0; epf < max_epfs; epf++) { if (!(epc->function_num_map & BIT(epf))) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 03b96798f858..7a66a2f815dc 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -131,6 +131,12 @@ #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 /* + * Endpoint PF Registers + */ +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) + +/* * Root Port Registers (PCI configuration space for the root port function) */ #define CDNS_PCIE_RP_BASE 0x00200000 |