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author | Bjorn Helgaas <bhelgaas@google.com> | 2018-06-07 00:10:05 +0300 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2018-06-07 00:10:05 +0300 |
commit | 08b5b2f7831a5378434bd8cc19e9239f3a3b6134 (patch) | |
tree | 1551044a0af2fee3233e3578fb000604a27d0ae1 /drivers/pci | |
parent | d7e02c08a93bbd3da1f3fd98d164c9b69a072b3a (diff) | |
parent | af8bb9f89838249872240f258e67774ccbcc5970 (diff) | |
download | linux-08b5b2f7831a5378434bd8cc19e9239f3a3b6134.tar.xz |
Merge branch 'pci/aspm'
- disable ASPM L1.2 substate if we don't have LTR (Bjorn Helgaas)
- respect platform ownership of LTR (Bjorn Helgaas)
* pci/aspm:
PCI/ACPI: Request LTR control from platform before using it
PCI/ASPM: Disable ASPM L1.2 Substate if we don't have LTR
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/pcie/aspm.c | 9 | ||||
-rw-r--r-- | drivers/pci/probe.c | 5 |
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index f76eb7704f64..c687c817b47d 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -400,6 +400,15 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, info->l1ss_cap = 0; return; } + + /* + * If we don't have LTR for the entire path from the Root Complex + * to this device, we can't use ASPM L1.2 because it relies on the + * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18. + */ + if (!pdev->ltr_path) + info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; + pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, &info->l1ss_ctl1); pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index ac91b6fd0bcd..cc1688d75664 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -554,6 +554,7 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) bridge->native_aer = 1; bridge->native_hotplug = 1; bridge->native_pme = 1; + bridge->native_ltr = 1; return bridge; } @@ -1954,9 +1955,13 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev) static void pci_configure_ltr(struct pci_dev *dev) { #ifdef CONFIG_PCIEASPM + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); u32 cap; struct pci_dev *bridge; + if (!host->native_ltr) + return; + if (!pci_is_pcie(dev)) return; |