diff options
author | Jiang Liu <jiang.liu@linux.intel.com> | 2014-11-12 14:11:25 +0300 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2014-11-23 15:01:47 +0300 |
commit | 38b6a1cf3e4df0a3267c01fab699ab65d58690f4 (patch) | |
tree | e6ff598d474183f2c7af3b17ef490ccdb526eb62 /drivers/pci | |
parent | aeeb59657c35da64068336c20068da237f41ab76 (diff) | |
download | linux-38b6a1cf3e4df0a3267c01fab699ab65d58690f4.tar.xz |
PCI/MSI: Move cached entry functions to irq core
Required to support non PCI based MSI.
[ tglx: Extracted from Jiangs patch series ]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/Kconfig | 1 | ||||
-rw-r--r-- | drivers/pci/msi.c | 18 |
2 files changed, 1 insertions, 18 deletions
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 893503fa1782..82f95f4512f8 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -4,6 +4,7 @@ config PCI_MSI bool "Message Signaled Interrupts (MSI and MSI-X)" depends on PCI + select GENERIC_MSI_IRQ help This allows device drivers to enable MSI (Message Signaled Interrupts). Message Signaled Interrupts enable a device to diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index b5bf2f641770..103700e127bf 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -290,24 +290,6 @@ void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) } } -void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) -{ - /* Assert that the cache is valid, assuming that - * valid messages are not all-zeroes. */ - BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | - entry->msg.data)); - - *msg = entry->msg; -} - -void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) -{ - struct msi_desc *entry = irq_get_msi_desc(irq); - - __get_cached_msi_msg(entry, msg); -} -EXPORT_SYMBOL_GPL(get_cached_msi_msg); - void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) { if (entry->dev->current_state != PCI_D0) { |