diff options
| author | Sinan Kaya <okaya@codeaurora.org> | 2017-02-17 01:01:45 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-02-17 23:00:33 +0300 |
| commit | 33be632b8443b6ac74aa293504f430604fb9abeb (patch) | |
| tree | c77f634fffe435139df1119fcd599252bc4bf1fa /drivers/pci/quirks.c | |
| parent | 5b0948dfe138f0837699f46f5877f4f81c252dac (diff) | |
| download | linux-33be632b8443b6ac74aa293504f430604fb9abeb.tar.xz | |
PCI: Add ACS quirk for Qualcomm QDF2400 and QDF2432
The Qualcomm QDF2xxx root ports don't advertise an ACS capability, but they
do provide ACS-like features to disable peer transactions and validate bus
numbers in requests.
To be specific:
* Hardware supports source validation but it will report the issue as
Completer Abort instead of ACS Violation.
* Hardware doesn't support peer-to-peer and each root port is a root
complex with unique segment numbers.
* It is not possible for one root port to pass traffic to the other root
port. All PCIe transactions are terminated inside the root port.
Add an ACS quirk for the QDF2400 and QDF2432 products.
[bhelgaas: changelog]
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Diffstat (limited to 'drivers/pci/quirks.c')
| -rw-r--r-- | drivers/pci/quirks.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index a0b3cd5726dc..29b75d7057c4 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4136,6 +4136,26 @@ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) } /* + * These QCOM root ports do provide ACS-like features to disable peer + * transactions and validate bus numbers in requests, but do not provide an + * actual PCIe ACS capability. Hardware supports source validation but it + * will report the issue as Completer Abort instead of ACS Violation. + * Hardware doesn't support peer-to-peer and each root port is a root + * complex with unique segment numbers. It is not possible for one root + * port to pass traffic to another root port. All PCIe transactions are + * terminated inside the root port. + */ +static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) +{ + u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); + int ret = acs_flags & ~flags ? 0 : 1; + + dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret); + + return ret; +} + +/* * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and @@ -4291,6 +4311,9 @@ static const struct pci_dev_acs_enabled { /* I219 */ { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, + /* QCOM QDF2xxx root ports */ + { 0x17cb, 0x400, pci_quirk_qcom_rp_acs }, + { 0x17cb, 0x401, pci_quirk_qcom_rp_acs }, /* Intel PCH root ports */ { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, |