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author | Bjorn Helgaas <bhelgaas@google.com> | 2018-01-31 19:10:26 +0300 |
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committer | Bjorn Helgaas <helgaas@kernel.org> | 2018-01-31 19:10:26 +0300 |
commit | 3ea8bc3326e1e88c0dc0b9bc8697d66eb69bf9a4 (patch) | |
tree | ca4337557d8ce1e849df3755d05d76f87e7b1f9e /drivers/pci/probe.c | |
parent | 86e99150c3ce4726d4f15c64f535b903a66fa76f (diff) | |
parent | 7d8e7d19b095ae70b1ca483ca36e7985a108abe5 (diff) | |
download | linux-3ea8bc3326e1e88c0dc0b9bc8697d66eb69bf9a4.tar.xz |
Merge branch 'pci/aspm' into next
* pci/aspm:
PCI/ASPM: Unexport internal ASPM interfaces
PCI/ASPM: Enable Latency Tolerance Reporting when supported
PCI/ASPM: Calculate LTR_L1.2_THRESHOLD from device characteristics
Diffstat (limited to 'drivers/pci/probe.c')
-rw-r--r-- | drivers/pci/probe.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 14e0ea1ff38b..3761b1303529 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1875,6 +1875,38 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev) } } +static void pci_configure_ltr(struct pci_dev *dev) +{ +#ifdef CONFIG_PCIEASPM + u32 cap; + struct pci_dev *bridge; + + if (!pci_is_pcie(dev)) + return; + + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (!(cap & PCI_EXP_DEVCAP2_LTR)) + return; + + /* + * Software must not enable LTR in an Endpoint unless the Root + * Complex and all intermediate Switches indicate support for LTR. + * PCIe r3.1, sec 6.18. + */ + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) + dev->ltr_path = 1; + else { + bridge = pci_upstream_bridge(dev); + if (bridge && bridge->ltr_path) + dev->ltr_path = 1; + } + + if (dev->ltr_path) + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); +#endif +} + static void pci_configure_device(struct pci_dev *dev) { struct hotplug_params hpp; @@ -1883,6 +1915,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_mps(dev); pci_configure_extended_tags(dev, NULL); pci_configure_relaxed_ordering(dev); + pci_configure_ltr(dev); memset(&hpp, 0, sizeof(hpp)); ret = pci_get_hp_params(dev, &hpp); |