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| author | Harvey Harrison <harvey.harrison@gmail.com> | 2008-03-04 06:09:46 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2008-04-21 08:47:09 +0400 |
| commit | 66bef8c059015ba2b36bb5759080336feb01e680 (patch) | |
| tree | 9060b134ba07e052bf40e0fbe641dfaa86bcbd9d /drivers/pci/hotplug/shpchp.h | |
| parent | ca99eb8c2d56bdfff0161388b81e641f4e039b3f (diff) | |
| download | linux-66bef8c059015ba2b36bb5759080336feb01e680.tar.xz | |
PCI: replace remaining __FUNCTION__ occurrences
__FUNCTION__ is gcc-specific, use __func__
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci/hotplug/shpchp.h')
| -rw-r--r-- | drivers/pci/hotplug/shpchp.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h index 37ed0884b972..f66e8d6315ab 100644 --- a/drivers/pci/hotplug/shpchp.h +++ b/drivers/pci/hotplug/shpchp.h @@ -234,7 +234,7 @@ static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device) return slot; } - err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device); + err("%s: slot (device=0x%x) not found\n", __func__, device); return NULL; } @@ -268,7 +268,7 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot) pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg); perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK; if (perr_set) { - dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set); + dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__func__ , perr_set); pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); } @@ -277,7 +277,7 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot) pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); rse_set = pcix_mem_base_reg & RSE_MASK; if (rse_set) { - dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ ); + dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__func__ ); pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); } |