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authorBjorn Helgaas <bhelgaas@google.com>2021-09-02 22:56:47 +0300
committerBjorn Helgaas <bhelgaas@google.com>2021-09-02 22:56:47 +0300
commit2b5a949eea282d03d1ace935936b1f73c5dd6cd7 (patch)
treeb8f08b97e9453dee472ea6bb62362aad228d3097 /drivers/pci/controller/cadence/pcie-cadence-ep.c
parent540267e236dd66fc3cb7429c8e88e3077f9a735b (diff)
parent7c52009d94ab561e70cb72e007a6076f20451f85 (diff)
downloadlinux-2b5a949eea282d03d1ace935936b1f73c5dd6cd7.tar.xz
Merge branch 'remotes/lorenzo/pci/cadence'
- Convert bool in structs to bitfield (Kishon Vijay Abraham I) - Work around J7200 non-PCIe SERDES lane electrical issue that prevents PCIe link training (Nadeem Athani) - Add J7200 PCIe support to j721e (Kishon Vijay Abraham I) - Add AM64 PCIe support to j721e (Kishon Vijay Abraham I) - Add J7200 and AM64 device IDs to endpoint test (Kishon Vijay Abraham I) * remotes/lorenzo/pci/cadence: misc: pci_endpoint_test: Add deviceID for AM64 and J7200 PCI: j721e: Add PCIe support for AM64 PCI: j721e: Add PCIe support for J7200 PCI: cadence: Add quirk flag to set minimum delay in LTSSM Detect.Quiet state PCI: cadence: Use bitfield for *quirk_retrain_flag* instead of bool
Diffstat (limited to 'drivers/pci/controller/cadence/pcie-cadence-ep.c')
-rw-r--r--drivers/pci/controller/cadence/pcie-cadence-ep.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index 897cdde02bd8..dd7df1ac7fda 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -623,6 +623,10 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
/* Reserve region 0 for IRQs */
set_bit(0, &ep->ob_region_map);
+
+ if (ep->quirk_detect_quiet_flag)
+ cdns_pcie_detect_quiet_min_delay_set(&ep->pcie);
+
spin_lock_init(&ep->lock);
return 0;