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| author | Jon Mason <jon.mason@intel.com> | 2013-11-02 02:08:19 +0400 |
|---|---|---|
| committer | Jon Mason <jon.mason@intel.com> | 2013-11-20 20:57:33 +0400 |
| commit | 58b889206ea4ba75a57986e223da647f91ba1a19 (patch) | |
| tree | 82c7010bc3f2bf9258a97efa631768ed15a55d6d /drivers/ntb | |
| parent | dcf81964e129da6140ff98a1a772044c62a7aa2e (diff) | |
| download | linux-58b889206ea4ba75a57986e223da647f91ba1a19.tar.xz | |
NTB: Document HW errata
Add a comment describing the necessary ordering of modifications to the
NTB Limit and Base registers.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Diffstat (limited to 'drivers/ntb')
| -rw-r--r-- | drivers/ntb/ntb_hw.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/ntb/ntb_hw.c b/drivers/ntb/ntb_hw.c index fa97948e66ad..391c377a5d38 100644 --- a/drivers/ntb/ntb_hw.c +++ b/drivers/ntb/ntb_hw.c @@ -689,6 +689,12 @@ static int ntb_xeon_setup(struct ntb_device *ndev) */ writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base + SNB_PBAR4LMT_OFFSET); + /* HW errata on the Limit registers. They can only be + * written when the base register is 4GB aligned and + * < 32bit. This should already be the case based on the + * driver defaults, but write the Limit registers first + * just in case. + */ } else { ndev->limits.max_mw = SNB_MAX_MW; @@ -707,6 +713,12 @@ static int ntb_xeon_setup(struct ntb_device *ndev) * something silly */ writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET); + /* HW errata on the Limit registers. They can only be + * written when the base register is 4GB aligned and + * < 32bit. This should already be the case based on the + * driver defaults, but write the Limit registers first + * just in case. + */ } /* The Xeon errata workaround requires setting SBAR Base |