diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2014-08-29 00:53:23 +0400 |
|---|---|---|
| committer | Jon Mason <jdmason@kudzu.us> | 2014-10-17 15:08:51 +0400 |
| commit | ab760a0c5667519b375ea9c5ab3a23501c4817ef (patch) | |
| tree | 29d2b7dd165287dd635ff4b320fcb6a9dc5a7eae /drivers/ntb/ntb_regs.h | |
| parent | 069684e888da73f175da0f10fe26da4f450d8c18 (diff) | |
| download | linux-ab760a0c5667519b375ea9c5ab3a23501c4817ef.tar.xz | |
ntb: Adding split BAR support for Haswell platforms
On the Haswell platform, a split BAR option to allow creation of 2
32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this
new option.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
Diffstat (limited to 'drivers/ntb/ntb_regs.h')
| -rw-r--r-- | drivers/ntb/ntb_regs.h | 31 |
1 files changed, 23 insertions, 8 deletions
diff --git a/drivers/ntb/ntb_regs.h b/drivers/ntb/ntb_regs.h index 07872057c76e..f028ff81fd77 100644 --- a/drivers/ntb/ntb_regs.h +++ b/drivers/ntb/ntb_regs.h @@ -57,6 +57,7 @@ #define SNB_MAX_DB_BITS 15 #define SNB_LINK_DB 15 #define SNB_DB_BITS_PER_VEC 5 +#define HSX_SPLITBAR_MAX_MW 3 #define SNB_MAX_MW 2 #define SNB_ERRATA_MAX_MW 1 @@ -72,15 +73,20 @@ #define SNB_PBAR2LMT_OFFSET 0x0000 #define SNB_PBAR4LMT_OFFSET 0x0008 +#define SNB_PBAR5LMT_OFFSET 0x000C #define SNB_PBAR2XLAT_OFFSET 0x0010 #define SNB_PBAR4XLAT_OFFSET 0x0018 +#define SNB_PBAR5XLAT_OFFSET 0x001C #define SNB_SBAR2LMT_OFFSET 0x0020 #define SNB_SBAR4LMT_OFFSET 0x0028 +#define SNB_SBAR5LMT_OFFSET 0x002C #define SNB_SBAR2XLAT_OFFSET 0x0030 #define SNB_SBAR4XLAT_OFFSET 0x0038 +#define SNB_SBAR5XLAT_OFFSET 0x003C #define SNB_SBAR0BASE_OFFSET 0x0040 #define SNB_SBAR2BASE_OFFSET 0x0048 #define SNB_SBAR4BASE_OFFSET 0x0050 +#define SNB_SBAR5BASE_OFFSET 0x0054 #define SNB_NTBCNTL_OFFSET 0x0058 #define SNB_SBDF_OFFSET 0x005C #define SNB_PDOORBELL_OFFSET 0x0060 @@ -96,12 +102,18 @@ #define SNB_B2B_XLAT_OFFSETL 0x0144 #define SNB_B2B_XLAT_OFFSETU 0x0148 -#define SNB_MBAR01_USD_ADDR 0x000000210000000CULL -#define SNB_MBAR23_USD_ADDR 0x000000410000000CULL -#define SNB_MBAR45_USD_ADDR 0x000000810000000CULL -#define SNB_MBAR01_DSD_ADDR 0x000000200000000CULL -#define SNB_MBAR23_DSD_ADDR 0x000000400000000CULL -#define SNB_MBAR45_DSD_ADDR 0x000000800000000CULL +/* + * The addresses are setup so the 32bit BARs can function. Thus + * the addresses are all in 32bit space + */ +#define SNB_MBAR01_USD_ADDR 0x000000002100000CULL +#define SNB_MBAR23_USD_ADDR 0x000000004100000CULL +#define SNB_MBAR4_USD_ADDR 0x000000008100000CULL +#define SNB_MBAR5_USD_ADDR 0x00000000A100000CULL +#define SNB_MBAR01_DSD_ADDR 0x000000002000000CULL +#define SNB_MBAR23_DSD_ADDR 0x000000004000000CULL +#define SNB_MBAR4_DSD_ADDR 0x000000008000000CULL +#define SNB_MBAR5_DSD_ADDR 0x00000000A000000CULL #define BWD_MSIX_CNT 34 #define BWD_MAX_SPADS 16 @@ -150,13 +162,16 @@ #define NTB_CNTL_LINK_DISABLE (1 << 1) #define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2) #define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4) -#define NTB_CNTL_S2P_BAR45_SNOOP (1 << 6) -#define NTB_CNTL_P2S_BAR45_SNOOP (1 << 8) +#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6) +#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8) +#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12) +#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14) #define BWD_CNTL_LINK_DOWN (1 << 16) #define NTB_PPD_OFFSET 0x00D4 #define SNB_PPD_CONN_TYPE 0x0003 #define SNB_PPD_DEV_TYPE 0x0010 +#define SNB_PPD_SPLIT_BAR (1 << 6) #define BWD_PPD_INIT_LINK 0x0008 #define BWD_PPD_CONN_TYPE 0x0300 #define BWD_PPD_DEV_TYPE 0x1000 |