diff options
| author | Arend van Spriel <arend@broadcom.com> | 2014-01-06 15:40:43 +0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2014-01-07 00:48:02 +0400 |
| commit | 3bd44d991f1906ee71807e07b388d9d2d94b7f7a (patch) | |
| tree | b37f9e83ee7c766e88e2d549f2df297f4d953ff7 /drivers/net | |
| parent | af35f55f94595c34076b7bf1cbe0087429d1ae5b (diff) | |
| download | linux-3bd44d991f1906ee71807e07b388d9d2d94b7f7a.tar.xz | |
brcmfmac: correct detection of save&restore device capability
The detection of the save&restore capability in brcmf_sdio_sr_capable()
is only valid for certain chipsets. This patch should cover it for all
chipsets currently supported.
Reviewed-by: Hante Meuleman <meuleman@broadcom.com>
Reviewed-by: Franky Lin <frankyl@broadcom.com>
Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c | 29 |
1 files changed, 22 insertions, 7 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c index 270cf9bed65d..ae5f040edb1c 100644 --- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c +++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c @@ -3384,7 +3384,8 @@ err: static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus) { - u32 addr, reg; + u32 addr, reg, pmu_cc3_mask = ~0; + int err; brcmf_dbg(TRACE, "Enter\n"); @@ -3392,13 +3393,27 @@ static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus) if (bus->ci->pmurev < 17) return false; - /* read PMU chipcontrol register 3*/ - addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr); - brcmf_sdiod_regwl(bus->sdiodev, addr, 3, NULL); - addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data); - reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL); + switch (bus->ci->chip) { + case BCM43241_CHIP_ID: + case BCM4335_CHIP_ID: + case BCM4339_CHIP_ID: + /* read PMU chipcontrol register 3 */ + addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr); + brcmf_sdiod_regwl(bus->sdiodev, addr, 3, NULL); + addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data); + reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL); + return (reg & pmu_cc3_mask) != 0; + default: + addr = CORE_CC_REG(bus->ci->c_inf[0].base, pmucapabilities_ext); + reg = brcmf_sdiod_regrl(bus->sdiodev, addr, &err); + if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0) + return false; - return (bool)reg; + addr = CORE_CC_REG(bus->ci->c_inf[0].base, retention_ctl); + reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL); + return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK | + PMU_RCTL_LOGIC_DISABLE_MASK)) == 0; + } } static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) |