diff options
| author | Tzu-En Huang <tehuang@realtek.com> | 2020-06-16 12:16:22 +0300 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2020-07-15 12:06:55 +0300 |
| commit | 58eb40c921a2b08ad3a2dff82ee7d965aadbcfee (patch) | |
| tree | 4380ae0c2a985098b1ca25a27e9812521d1c401e /drivers/net/wireless/realtek/rtw88/rtw8821c.h | |
| parent | 6cf2086fd099bcc81b872175b60a7ba2228e407c (diff) | |
| download | linux-58eb40c921a2b08ad3a2dff82ee7d965aadbcfee.tar.xz | |
rtw88: 8821c: add set channel support
8821c is capable of 2.4G and 5G.
Implement rtw_chip_ops::set_channel() to set 2G and 5G channels.
This includes MAC, BB and RF related settings.
Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Tzu-En Huang <tehuang@realtek.com>
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200616091625.26489-5-yhchuang@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw88/rtw8821c.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw88/rtw8821c.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821c.h b/drivers/net/wireless/realtek/rtw88/rtw8821c.h index 1c357e2b099b..2d33f6e50cea 100644 --- a/drivers/net/wireless/realtek/rtw88/rtw8821c.h +++ b/drivers/net/wireless/realtek/rtw88/rtw8821c.h @@ -161,6 +161,7 @@ _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) #define REG_ADCCLK 0x8ac #define REG_ADC160 0x8c4 #define REG_ADC40 0x8c8 +#define REG_CHFIR 0x8f0 #define REG_CDDTXP 0x93c #define REG_TXPSEL1 0x940 #define REG_ACBB0 0x948 @@ -172,7 +173,9 @@ _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) #define REG_TXSF6 0xa28 #define REG_RXDESC 0xa2c #define REG_ENTXCCK 0xa80 +#define REG_TXFILTER 0xaac #define REG_AGCTR_A 0xc08 +#define REG_TXSCALE_A 0xc1c #define REG_TXDFIR 0xc20 #define REG_RXIGI_A 0xc50 #define REG_TRSW 0xca0 @@ -185,4 +188,16 @@ _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) #define REG_ANTWT 0x1904 #define REG_IQKFAILMSK 0x1bf0 +#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) +#define RF18_BAND_2G (0) +#define RF18_BAND_5G (BIT(16) | BIT(8)) +#define RF18_CHANNEL_MASK (MASKBYTE0) +#define RF18_RFSI_MASK (BIT(18) | BIT(17)) +#define RF18_RFSI_GE (BIT(17)) +#define RF18_RFSI_GT (BIT(18)) +#define RF18_BW_MASK (BIT(11) | BIT(10)) +#define RF18_BW_20M (BIT(11) | BIT(10)) +#define RF18_BW_40M (BIT(11)) +#define RF18_BW_80M (BIT(10)) + #endif |