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authorWey-Yi Guy <wey-yi.w.guy@intel.com>2011-04-02 03:29:52 +0400
committerWey-Yi Guy <wey-yi.w.guy@intel.com>2011-04-08 19:01:37 +0400
commit8ff84a2c99bc7f5f22d9d2b5365d821ce4f7a8f9 (patch)
tree0a877d809d941b012ced38f850eb8345ea5ae100 /drivers/net/wireless/iwlwifi/iwl-prph.h
parent15ade3ca647d95611814333cfe0885fd0184481e (diff)
downloadlinux-8ff84a2c99bc7f5f22d9d2b5365d821ce4f7a8f9.tar.xz
iwlagn: more cleanup to remove unused reference
More cleanup code, no functional changes Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-prph.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-prph.h16
1 files changed, 3 insertions, 13 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h
index c960195df989..f00d188b2cfc 100644
--- a/drivers/net/wireless/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/iwlwifi/iwl-prph.h
@@ -107,17 +107,7 @@
* device. A queue maps to only one (selectable by driver) Tx DMA channel,
* but one DMA channel may take input from several queues.
*
- * Tx DMA FIFOs have dedicated purposes. For 4965, they are used as follows
- * (cf. default_queue_to_tx_fifo in iwl-4965.c):
- *
- * 0 -- EDCA BK (background) frames, lowest priority
- * 1 -- EDCA BE (best effort) frames, normal priority
- * 2 -- EDCA VI (video) frames, higher priority
- * 3 -- EDCA VO (voice) and management frames, highest priority
- * 4 -- Commands (e.g. RXON, etc.)
- * 5 -- unused (HCCA)
- * 6 -- unused (HCCA)
- * 7 -- not used by driver (device-internal only)
+ * Tx DMA FIFOs have dedicated purposes.
*
* For 5000 series and up, they are used differently
* (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
@@ -151,7 +141,7 @@
* Tx completion may end up being out-of-order).
*
* The driver must maintain the queue's Byte Count table in host DRAM
- * (struct iwl4965_sched_queue_byte_cnt_tbl) for this mode.
+ * for this mode.
* This mode does not support fragmentation.
*
* 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
@@ -164,7 +154,7 @@
*
* Driver controls scheduler operation via 3 means:
* 1) Scheduler registers
- * 2) Shared scheduler data base in internal 4956 SRAM
+ * 2) Shared scheduler data base in internal SRAM
* 3) Shared data in host DRAM
*
* Initialization: