diff options
| author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2012-11-13 10:03:53 +0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2012-11-16 23:29:11 +0400 |
| commit | 57527f8d4d71b5167a02fb6713857f55d3974748 (patch) | |
| tree | d01ec106619e598a02656f9d3d67dd027ff51f9c /drivers/net/wireless/ath/ath9k/ar9003_hw.c | |
| parent | f3684343060636491d337e716f08834523cef722 (diff) | |
| download | linux-57527f8d4d71b5167a02fb6713857f55d3974748.tar.xz | |
ath9k_hw: Program filter coefficients correctly
2484 Mhz (Japan) usage requires filter coefficients to
be programmed in the CCK TX FIR registers. This is required
for AR9331, AR9485 and AR9462. Fix this and also remove
a few useless macros and a duplicate variable.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_hw.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_hw.c | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index 0693cd95b746..74fd3977feeb 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c @@ -35,12 +35,6 @@ */ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) { -#define AR9462_BB_CTX_COEFJ(x) \ - ar9462_##x##_baseband_core_txfir_coeff_japan_2484 - -#define AR9462_BBC_TXIFR_COEFFJ \ - ar9462_2p0_baseband_core_txfir_coeff_japan_2484 - if (AR_SREV_9330_11(ah)) { /* mac */ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], @@ -70,6 +64,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9331_modes_lowest_ob_db_tx_gain_1p1); + /* Japan 2484 Mhz CCK */ + INIT_INI_ARRAY(&ah->iniCckfirJapan2484, + ar9331_1p1_baseband_core_txfir_coeff_japan_2484); + /* additional clock settings */ if (ah->is_clk_25mhz) INIT_INI_ARRAY(&ah->iniAdditional, @@ -106,6 +104,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9331_modes_lowest_ob_db_tx_gain_1p2); + /* Japan 2484 Mhz CCK */ + INIT_INI_ARRAY(&ah->iniCckfirJapan2484, + ar9331_1p2_baseband_core_txfir_coeff_japan_2484); + /* additional clock settings */ if (ah->is_clk_25mhz) INIT_INI_ARRAY(&ah->iniAdditional, @@ -180,6 +182,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9485_modes_lowest_ob_db_tx_gain_1_1); + /* Japan 2484 Mhz CCK */ + INIT_INI_ARRAY(&ah->iniCckfirJapan2484, + ar9485_1_1_baseband_core_txfir_coeff_japan_2484); + /* Load PCIE SERDES settings from INI */ /* Awake Setting */ @@ -229,9 +235,7 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ar9462_modes_fast_clock_2p0); INIT_INI_ARRAY(&ah->iniCckfirJapan2484, - AR9462_BB_CTX_COEFJ(2p0)); - - INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ); + ar9462_2p0_baseband_core_txfir_coeff_japan_2484); } else if (AR_SREV_9550(ah)) { /* mac */ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |