diff options
| author | Rajkumar Manoharan <rmanohar@qca.qualcomm.com> | 2011-10-13 09:30:38 +0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-10-14 22:48:22 +0400 |
| commit | 8ad74c4d8c5e26121f698f56595768b76d1bed81 (patch) | |
| tree | 62df91d520f4cddc6cca6d67123e97ed66d50a3c /drivers/net/wireless/ath/ath9k/ar9003_calib.c | |
| parent | 77a5a6648da6b90d6ba990bf03c59993cdd5a516 (diff) | |
| download | linux-8ad74c4d8c5e26121f698f56595768b76d1bed81.tar.xz | |
ath9k_hw: Cleanup Tx calibrations for AR9003 chips
Currently Tx IQ calibration is enabled by default for all AR9003
chips. But for AR9480, the calibration status should be read from
chip after processing ini. And also the carrier leak calibration
status is checked during init cal. As the init_cal is being called
for fast channel change too, the tx_cl status only be read after
full reset. Hence moving that into process ini function.
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_calib.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_calib.c | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c index 5f406382677e..3506e7bd36eb 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c @@ -906,15 +906,13 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, struct ath_common *common = ath9k_hw_common(ah); struct ath9k_hw_cal_data *caldata = ah->caldata; bool txiqcal_done = false, txclcal_done = false; - bool is_reusable = true, txclcal_enabled; + bool is_reusable = true; + int i, j; u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0, AR_PHY_CL_TAB_1, AR_PHY_CL_TAB_2 }; - txclcal_enabled = !!(REG_READ(ah, AR_PHY_CL_CAL_CTL) & - AR_PHY_CL_CAL_ENABLE); - - if (txclcal_enabled) { + if (ah->enabled_cals & TX_CL_CAL) { if (caldata && caldata->done_txclcal_once) REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); @@ -923,6 +921,9 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, AR_PHY_CL_CAL_ENABLE); } + if (!(ah->enabled_cals & TX_IQ_CAL)) + goto skip_tx_iqcal; + /* Do Tx IQ Calibration */ REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1, AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, @@ -932,7 +933,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, * For AR9485 or later chips, TxIQ cal runs as part of * AGC calibration */ - if (AR_SREV_9485_OR_LATER(ah) && !AR_SREV_9340(ah)) { + if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) { if (caldata && !caldata->done_txiqcal_once) REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL); @@ -940,13 +941,14 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL); txiqcal_done = true; - } else { - txiqcal_done = ar9003_hw_tx_iq_cal_run(ah); - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); - udelay(5); - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); + goto skip_tx_iqcal; } + txiqcal_done = ar9003_hw_tx_iq_cal_run(ah); + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); + udelay(5); + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); +skip_tx_iqcal: /* Calibrate the AGC */ REG_WRITE(ah, AR_PHY_AGC_CONTROL, REG_READ(ah, AR_PHY_AGC_CONTROL) | @@ -966,8 +968,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, ar9003_hw_tx_iq_cal_reload(ah); #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) - if (caldata && txclcal_enabled) { - int i, j; + if (caldata && (ah->enabled_cals & TX_CL_CAL)) { txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_CLC_SUCCESS); if (caldata->done_txclcal_once) { |