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authorRomain Perier <romain.perier@gmail.com>2015-08-23 12:32:37 +0300
committerStephen Boyd <sboyd@codeaurora.org>2015-09-10 23:55:30 +0300
commit3bba75a2ec32bd5fa7024a4de3b8cf9ee113a76a (patch)
tree33c33a65294d3e3ee6907fffc2e8fdab3fa070eb /drivers/net/wireless/ath/ath10k/mac.c
parent1166160ab531198f7abc773992c0e04d0f9b7600 (diff)
downloadlinux-3bba75a2ec32bd5fa7024a4de3b8cf9ee113a76a.tar.xz
clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188
Now that the rockchip clock subsystem does clock gating with GPIO banks, these are no longer enabled once during probe and no longer stay enabled for eternity. When all these clocks are disabled, the parent clock pclk_peri might be disabled too, as no other child claims it. So, we need to add pclk_peri to the critical clocks. Signed-off-by: Romain Perier <romain.perier@gmail.com> Tested-by: Michael Niewoehner <linux@mniewoehner.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/net/wireless/ath/ath10k/mac.c')
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