diff options
| author | Ben Hutchings <bhutchings@solarflare.com> | 2009-11-28 08:36:12 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-11-29 10:58:55 +0300 |
| commit | 0228f5cdb03f6656247cf2876f9f4f8fc213ffd6 (patch) | |
| tree | a8541286a79b2172dbf3543796e94d0f395d671f /drivers/net/sfc/falcon.c | |
| parent | daeda6309e1382819a8f8bab548560742ac26cc2 (diff) | |
| download | linux-0228f5cdb03f6656247cf2876f9f4f8fc213ffd6.tar.xz | |
sfc: Move descriptor cache base addresses to struct efx_nic_type
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/falcon.c')
| -rw-r--r-- | drivers/net/sfc/falcon.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c index 7c9c9c935957..539d0223b434 100644 --- a/drivers/net/sfc/falcon.c +++ b/drivers/net/sfc/falcon.c @@ -45,11 +45,9 @@ */ #define TX_DC_ENTRIES 16 #define TX_DC_ENTRIES_ORDER 1 -#define TX_DC_BASE 0x130000 #define RX_DC_ENTRIES 64 #define RX_DC_ENTRIES_ORDER 3 -#define RX_DC_BASE 0x100000 static const unsigned int /* "Large" EEPROM device: Atmel AT25640 or similar @@ -3043,9 +3041,11 @@ int falcon_init_nic(struct efx_nic *efx) return rc; /* Set positions of descriptor caches in SRAM. */ - EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); + EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, + efx->type->tx_dc_base / 8); efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); - EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); + EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, + efx->type->rx_dc_base / 8); efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); /* Set TX descriptor cache size. */ @@ -3248,6 +3248,8 @@ struct efx_nic_type falcon_a1_nic_type = { .rx_buffer_padding = 0x24, .max_interrupt_mode = EFX_INT_MODE_MSI, .phys_addr_channels = 4, + .tx_dc_base = 0x130000, + .rx_dc_base = 0x100000, }; struct efx_nic_type falcon_b0_nic_type = { @@ -3271,5 +3273,7 @@ struct efx_nic_type falcon_b0_nic_type = { .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy * interrupt handler only supports 32 * channels */ + .tx_dc_base = 0x130000, + .rx_dc_base = 0x100000, }; |