diff options
| author | Harini Katakam <harini.katakam@amd.com> | 2022-10-14 09:47:35 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-10-15 13:10:56 +0300 |
| commit | 0c9efbd5c50c64ead434960a404c9c9a097b0403 (patch) | |
| tree | 88bd5e90a54a2534651f31af4e6944f9a0f8ae4b /drivers/net/phy | |
| parent | 017e42540639a46fdf7c7f5ee647e0b7806c9013 (diff) | |
| download | linux-0c9efbd5c50c64ead434960a404c9c9a097b0403.tar.xz | |
net: phy: dp83867: Extend RX strap quirk for SGMII mode
When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4
register should be set. The former is already handled in
dp83867_config_init; add the latter in SGMII specific initialization.
Fixes: 2a10154abcb7 ("net: phy: dp83867: Add TI dp83867 phy")
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy')
| -rw-r--r-- | drivers/net/phy/dp83867.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 6939563d3b7c..417527f8bbf5 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -853,6 +853,14 @@ static int dp83867_config_init(struct phy_device *phydev) else val &= ~DP83867_SGMII_TYPE; phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); + + /* This is a SW workaround for link instability if RX_CTRL is + * not strapped to mode 3 or 4 in HW. This is required for SGMII + * in addition to clearing bit 7, handled above. + */ + if (dp83867->rxctrl_strap_quirk) + phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, + BIT(8)); } val = phy_read(phydev, DP83867_CFG3); |