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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2018-11-19 00:23:56 +0300
committerDavid S. Miller <davem@davemloft.net>2018-11-19 03:16:20 +0300
commitee336140864d069d95194e8a007827363bd36da4 (patch)
tree75b323f51801b90255cb93f3a913e77f8617be9f /drivers/net/phy/icplus.c
parent034289b2d7cf29c8ddb79cf73d4886edabcff05e (diff)
downloadlinux-ee336140864d069d95194e8a007827363bd36da4.tar.xz
net: phy: icplus: use the BIT macro where possible
This makes the code consistent by using the BIT() macro instead of manual bit-shifting for some of the fields. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/icplus.c')
-rw-r--r--drivers/net/phy/icplus.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index 3d3e9134c762..3ec470adde3d 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -36,11 +36,11 @@ MODULE_LICENSE("GPL");
/* IP101A/G - IP1001 */
#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
-#define IP1001_RXPHASE_SEL (1<<0) /* Add delay on RX_CLK */
-#define IP1001_TXPHASE_SEL (1<<1) /* Add delay on TX_CLK */
+#define IP1001_RXPHASE_SEL BIT(0) /* Add delay on RX_CLK */
+#define IP1001_TXPHASE_SEL BIT(1) /* Add delay on TX_CLK */
#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
-#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
+#define IP101A_G_APS_ON BIT(1) /* IP101A/G APS Mode bit */
#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
#define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */
#define IP101A_G_NO_IRQ BIT(11) /* IRQ's inactive */