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authorDavid Daney <david.daney@cavium.com>2011-09-30 16:17:48 +0400
committerDavid S. Miller <davem@davemloft.net>2011-10-01 02:54:08 +0400
commit76231e0297db30f1f0e947a02b42495e7d535d56 (patch)
treea0fbf2e596d01de7cfe3d7ea8447b3e72e775ec9 /drivers/net/phy/icplus.c
parent6fe3264945ee63292cdfb27b6e95bc52c603bb09 (diff)
downloadlinux-76231e0297db30f1f0e947a02b42495e7d535d56.tar.xz
netdev/phy/icplus: Use mdiobus_write() and mdiobus_read() for proper locking.
Usually you have to take the bus lock. Why not here too? I saw this when working on something else. Not even compile tested. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Greg Dietsche <Gregory.Dietsche@cuw.edu> Cc: "Uwe Kleine-Konig" <u.kleine-koenig@pengutronix.de> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/icplus.c')
-rw-r--r--drivers/net/phy/icplus.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index 6e344e59caf7..d66bd8d12599 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -49,36 +49,36 @@ static int ip175c_config_init(struct phy_device *phydev)
if (full_reset_performed == 0) {
/* master reset */
- err = phydev->bus->write(phydev->bus, 30, 0, 0x175c);
+ err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
if (err < 0)
return err;
/* ensure no bus delays overlap reset period */
- err = phydev->bus->read(phydev->bus, 30, 0);
+ err = mdiobus_read(phydev->bus, 30, 0);
/* data sheet specifies reset period is 2 msec */
mdelay(2);
/* enable IP175C mode */
- err = phydev->bus->write(phydev->bus, 29, 31, 0x175c);
+ err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
if (err < 0)
return err;
/* Set MII0 speed and duplex (in PHY mode) */
- err = phydev->bus->write(phydev->bus, 29, 22, 0x420);
+ err = mdiobus_write(phydev->bus, 29, 22, 0x420);
if (err < 0)
return err;
/* reset switch ports */
for (i = 0; i < 5; i++) {
- err = phydev->bus->write(phydev->bus, i,
- MII_BMCR, BMCR_RESET);
+ err = mdiobus_write(phydev->bus, i,
+ MII_BMCR, BMCR_RESET);
if (err < 0)
return err;
}
for (i = 0; i < 5; i++)
- err = phydev->bus->read(phydev->bus, i, MII_BMCR);
+ err = mdiobus_read(phydev->bus, i, MII_BMCR);
mdelay(2);