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authorMark Brown <broonie@sirena.org.uk>2007-02-19 23:15:40 +0300
committerJeff Garzik <jeff@garzik.org>2007-02-20 19:18:13 +0300
commit6aab44475a1355365f0a24abe6f8eb32185a701e (patch)
tree084fab50438559617142445b80059d901fc81cb8 /drivers/net/natsemi.c
parent68c90166e4aaa15ddcdd4778ad30bfb8b32534be (diff)
downloadlinux-6aab44475a1355365f0a24abe6f8eb32185a701e.tar.xz
natsemi: Support Aculab E1/T1 PMXc cPCI carrier cards
Aculab E1/T1 PMXc cPCI carrier card cards present a natsemi on the cPCI bus with an oversized EEPROM using a direct MII<->MII connection with no PHY. This patch adds a new device table entry supporting these cards. Signed-Off-By: Mark Brown <broonie@sirena.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/natsemi.c')
-rw-r--r--drivers/net/natsemi.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index 4e21f5510b90..adf29dd66798 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -244,6 +244,9 @@ enum {
MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
};
+enum {
+ NATSEMI_FLAG_IGNORE_PHY = 0x1,
+};
/* array of board data directly indexed by pci_tbl[x].driver_data */
static const struct {
@@ -251,10 +254,12 @@ static const struct {
unsigned long flags;
unsigned int eeprom_size;
} natsemi_pci_info[] __devinitdata = {
+ { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
{ "NatSemi DP8381[56]", 0, 24 },
};
static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
+ { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
{ PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ } /* terminate list */
};
@@ -811,7 +816,10 @@ static int __devinit natsemi_probe1 (struct pci_dev *pdev,
np->hands_off = 0;
np->intr_status = 0;
np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
- np->ignore_phy = 0;
+ if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
+ np->ignore_phy = 1;
+ else
+ np->ignore_phy = 0;
/* Initial port:
* - If configured to ignore the PHY set up for external.