diff options
| author | Nogah Frankel <nogahf@mellanox.com> | 2016-09-20 12:16:49 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-09-21 08:00:58 +0300 |
| commit | 9f7f797c1df40ee6c0329e9e53ea9ca0d224f55d (patch) | |
| tree | 42a4272d8d589e0174f704dd7f19d2044fccf88d /drivers/net/ethernet | |
| parent | 4bdcc6ca2158f43b1770e020f9b71ab8a808594f (diff) | |
| download | linux-9f7f797c1df40ee6c0329e9e53ea9ca0d224f55d.tar.xz | |
mlxsw: pci: Add lag related resources to resources query
Add max lag and max ports in lag resources to resources query.
Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Reviewed-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/core.h | 6 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/pci.c | 10 |
2 files changed, 15 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h index d2e32979319c..51f27a35749e 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.h +++ b/drivers/net/ethernet/mellanox/mlxsw/core.h @@ -269,8 +269,12 @@ struct mlxsw_driver { }; struct mlxsw_resources { - u8 max_span_valid:1; + u8 max_span_valid:1, + max_lag_valid:1, + max_ports_in_lag_valid:1; u8 max_span; + u8 max_lag; + u8 max_ports_in_lag; }; struct mlxsw_resources *mlxsw_core_resources_get(struct mlxsw_core *mlxsw_core); diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 1d1360c178bb..cb284eaeec39 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -1156,6 +1156,8 @@ mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, #define MLXSW_RESOURCES_TABLE_END_ID 0xffff #define MLXSW_MAX_SPAN_ID 0x2420 +#define MLXSW_MAX_LAG_ID 0x2520 +#define MLXSW_MAX_PORTS_IN_LAG_ID 0x2521 #define MLXSW_RESOURCES_QUERY_MAX_QUERIES 100 #define MLXSW_RESOURCES_PER_QUERY 32 @@ -1167,6 +1169,14 @@ static void mlxsw_pci_resources_query_parse(int id, u64 val, resources->max_span = val; resources->max_span_valid = 1; break; + case MLXSW_MAX_LAG_ID: + resources->max_lag = val; + resources->max_lag_valid = 1; + break; + case MLXSW_MAX_PORTS_IN_LAG_ID: + resources->max_ports_in_lag = val; + resources->max_ports_in_lag_valid = 1; + break; default: break; } |